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Searched refs:STM32_PLL_R_DIVISOR (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32g4.c68 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32g0_u0.c64 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32l4_l5_wb_wl.c83 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32f2_f4_f7.c100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_u5.c109 STM32_PLL_R_DIVISOR); in get_sysclk_frequency()
315 STM32_PLL_R_DIVISOR); in stm32_clock_control_get_subsys_rate()
583 __ASSERT_NO_MSG((STM32_PLL_R_DIVISOR == 1) || in set_up_plls()
584 (STM32_PLL_R_DIVISOR % 2 == 0)); in set_up_plls()
585 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h5.c104 STM32_PLL_R_DIVISOR); in get_sysclk_frequency()
299 STM32_PLL_R_DIVISOR); in stm32_clock_control_get_subsys_rate()
498 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR); in set_up_plls()
Dclock_stm32_ll_wba.c244 STM32_PLL_R_DIVISOR); in stm32_clock_control_get_subsys_rate()
427 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c573 STM32_PLL_R_DIVISOR);
865 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
Dclock_stm32_ll_common.c425 STM32_PLL_R_DIVISOR); in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h174 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1) macro