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Searched refs:STM32_PLL_Q_ENABLED (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f2_f4_f7.c107 #if STM32_PLL_Q_ENABLED in config_pll_sysclock()
Dclock_stm32_ll_common.c205 if (!IS_ENABLED(STM32_PLL_Q_ENABLED)) { in enabled_clock()
419 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED in stm32_clock_control_get_subsys_rate()
606 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED in set_up_plls()
Dclock_stm32_ll_wba.c57 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
419 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h5.c133 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
487 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c139 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
575 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c370 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
856 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h165 #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q) macro