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Searched refs:STM32_PLL_Q_DIVISOR (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f2_f4_f7.c112 pllq(STM32_PLL_Q_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_wba.c236 STM32_PLL_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
420 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR); in set_up_plls()
Dclock_stm32_ll_common.c424 STM32_PLL_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
607 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR)); in set_up_plls()
Dclock_stm32_ll_h5.c292 STM32_PLL_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
488 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR); in set_up_plls()
Dclock_stm32_ll_u5.c307 STM32_PLL_Q_DIVISOR); in stm32_clock_control_get_subsys_rate()
576 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c564 STM32_PLL_Q_DIVISOR);
857 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h166 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1) macro