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Searched refs:STM32_PLL_P_DIVISOR (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f2_f4_f7.c105 pllp(STM32_PLL_P_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_wba.c232 STM32_PLL_P_DIVISOR); in stm32_clock_control_get_subsys_rate()
417 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c76 STM32_PLL_P_DIVISOR)
240 STM32_PLL_P_DIVISOR); in get_hclk_frequency()
561 STM32_PLL_P_DIVISOR);
855 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
Dclock_stm32_ll_h5.c287 STM32_PLL_P_DIVISOR); in stm32_clock_control_get_subsys_rate()
488 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); in set_up_plls()
Dclock_stm32_ll_common.c409 STM32_PLL_P_DIVISOR); in stm32_clock_control_get_subsys_rate()
596 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR)); in set_up_plls()
Dclock_stm32_ll_u5.c303 STM32_PLL_P_DIVISOR); in stm32_clock_control_get_subsys_rate()
573 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); in set_up_plls()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h170 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1) macro