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Searched refs:STM32_PLL_M_DIVISOR (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f2_f4_f7.c103 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
110 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32g4.c66 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32g0_u0.c62 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_wba.c228 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
234 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
240 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
401 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in set_up_plls()
406 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_u5.c107 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
299 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
305 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
311 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
475 tmp = MIN(tmp / STM32_PLL_M_DIVISOR / 8000000, 16); in set_epod_booster()
552 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
557 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32l4_l5_wb_wl.c81 pllm(STM32_PLL_M_DIVISOR), in config_pll_sysclock()
Dclock_stm32_ll_h5.c102 STM32_PLL_M_DIVISOR, in get_sysclk_frequency()
284 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
290 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
296 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
464 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
471 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c74 STM32_PLL_M_DIVISOR,\
237 STM32_PLL_M_DIVISOR, in get_hclk_frequency()
556 STM32_PLL_M_DIVISOR,
562 STM32_PLL_M_DIVISOR,
568 STM32_PLL_M_DIVISOR,
575 STM32_PLL_M_DIVISOR,
831 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
838 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR);
Dclock_stm32_ll_common.c414 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
422 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
430 STM32_PLL_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h161 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) macro
177 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR