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Searched refs:SPI123_SEL (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pll2p_1.overlay23 <&rcc STM32_SRC_PLL2_P SPI123_SEL(1)>;
Dspi1_per_ck_d1ppre_1.overlay25 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
Dspi1_pllq_1_d1ppre_1.overlay25 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
Dspi1_per_ck_hse.overlay26 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
Dspi1_per_ck_hsi.overlay25 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
Dspi1_pll3p_1_d1ppre_4.overlay28 <&rcc STM32_SRC_PLL3_P SPI123_SEL(2)>;
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnucleo_h723zg.overlay17 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7_clock.h113 #define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG) macro
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7.dtsi427 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
438 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
449 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
490 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
504 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
518 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;