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Searched refs:SDRAM0_BASE (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
Dmemory.h14 #define SDRAM0_BASE 0x1a000000 macro
81 #define SDRAM0_BASE 0x1a000000 macro
Dlinker.ld87 org = SDRAM0_BASE,
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/
Dmemory.h15 #define SDRAM0_BASE 0x92400000 macro
85 #define SDRAM0_BASE 0x92400000 macro
Dlinker.ld87 org = SDRAM0_BASE,
/Zephyr-latest/soc/nxp/imx/imx8/adsp/
Dmemory.h15 #define SDRAM0_BASE 0x92400000 macro
85 #define SDRAM0_BASE 0x92400000 macro
Dlinker.ld87 org = SDRAM0_BASE,
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dmemory.h20 #define SDRAM0_BASE 0x92400000 macro
90 #define SDRAM0_BASE 0x92400000 macro
Dlinker.ld87 org = SDRAM0_BASE,
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/soc/
Dmemory.h13 #define SDRAM0_BASE (CONFIG_RT595_ADSP_DATA_MEM_ADDR) macro
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/
Dlinker.ld76 org = SDRAM0_BASE,
415 _heap_sentry = SDRAM0_BASE + SDRAM0_SIZE;
416 __stack = SDRAM0_BASE + SDRAM0_SIZE + CONFIG_RT595_ADSP_STACK_SIZE;