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Searched refs:REG_READ (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/drivers/interrupt_controller/
Dintc_wkpu_nxp_s32.c34 #define REG_READ(r) sys_read32(config->base + (r)) macro
65 REG_WRITE(WKPU_WISR(irq / 32U), REG_READ(WKPU_WISR(irq / 32U)) | irq_mask); in wkpu_nxp_s32_interrupt_handler()
119 reg_val = REG_READ(WKPU_WIREER(reg_idx)); in wkpu_nxp_s32_enable_interrupt()
127 reg_val = REG_READ(WKPU_WIFEER(reg_idx)); in wkpu_nxp_s32_enable_interrupt()
136 REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
137 REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) | mask); in wkpu_nxp_s32_enable_interrupt()
149 REG_WRITE(WKPU_WIREER(reg_idx), REG_READ(WKPU_WIREER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
150 REG_WRITE(WKPU_WIFEER(reg_idx), REG_READ(WKPU_WIFEER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
153 REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask); in wkpu_nxp_s32_disable_interrupt()
154 REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) & ~mask); in wkpu_nxp_s32_disable_interrupt()
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Dintc_eirq_nxp_s32.c39 #define REG_READ(r) sys_read32(config->base + (r)) macro
77 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask); in eirq_nxp_s32_interrupt_handler()
129 reg_val = REG_READ(SIUL2_IREER0); in eirq_nxp_s32_enable_interrupt()
137 reg_val = REG_READ(SIUL2_IFEER0); in eirq_nxp_s32_enable_interrupt()
146 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
147 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
157 REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
158 REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
161 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_disable_interrupt()
162 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_s32.c81 #define REG_READ(r) sys_read32(config->base + (r)) macro
122 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_HLK(1U)); in swt_lock()
125 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_lock()
138 if (FIELD_GET(SWT_CR_HLK_MASK, REG_READ(SWT_CR)) != 0U) { in swt_unlock()
142 } else if (FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR)) != 0U) { in swt_unlock()
146 if (!WAIT_FOR(FIELD_GET(SWT_CR_SLK_MASK, REG_READ(SWT_CR) != 0), in swt_unlock()
152 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_SLK(1U)); in swt_unlock()
162 return (uint16_t)((FIELD_GET(SWT_SK_SK_MASK, REG_READ(SWT_SK)) * 17U) + 3U); in swt_gen_service_key()
182 reg_val = REG_READ(SWT_CR); in swt_nxp_s32_setup()
198 REG_WRITE(SWT_CR, REG_READ(SWT_CR) | SWT_CR_WEN(1U)); in swt_nxp_s32_setup()
[all …]
Dxt_wdt_esp32.c104 uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG); in esp32_xt_wdt_isr()
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc_irq.c59 status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) & in soc_intr_get_next_source()
68 status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) & in soc_intr_get_next_source()
77 status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) & in soc_intr_get_next_source()
/Zephyr-latest/soc/nxp/s32/common/
Dmc_rgm.c60 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
71 timeout = !WAIT_FOR(REG_READ(reg) == 0U, MC_RGM_TIMEOUT_US, REG_WRITE(reg, 0xffffffff)); in mc_rgm_clear_reset_status()
86 rst_status = REG_READ(MC_RGM_FES); in mc_rgm_init()
97 rst_status = REG_READ(MC_RGM_DES); in mc_rgm_init()
Dmc_me.c79 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
/Zephyr-latest/soc/espressif/esp32c2/
Dsoc_irq.c57 status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) & in soc_intr_get_next_source()
63 status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) & in soc_intr_get_next_source()
/Zephyr-latest/soc/espressif/esp32c3/
Dsoc_irq.c57 status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_0_REG) & in soc_intr_get_next_source()
63 status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_1_REG) & in soc_intr_get_next_source()
/Zephyr-latest/drivers/ethernet/
Deth_dwmac.c398 status = REG_READ(DMA_CHn_STATUS(ch)); in dwmac_dma_irq()
421 status = REG_READ(MAC_IRQ_STATUS); in dwmac_mac_irq()
430 status = REG_READ(MTL_IRQ_STATUS); in dwmac_mtl_irq()
441 irq_status = REG_READ(DMA_IRQ_STATUS); in dwmac_isr()
489 reg_val = REG_READ(MAC_PKT_FILTER); in dwmac_set_config()
544 reg_val = REG_READ(DMA_CHn_TX_CTRL(0)); in dwmac_iface_init()
546 reg_val = REG_READ(DMA_CHn_RX_CTRL(0)); in dwmac_iface_init()
548 reg_val = REG_READ(MAC_CONF); in dwmac_iface_init()
576 reg_val = REG_READ(MAC_VERSION); in dwmac_probe()
584 while (REG_READ(DMA_MODE) & DMA_MODE_SWR) { in dwmac_probe()
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Deth_dwmac_priv.h76 #define REG_READ(r) sys_read32(p->base_addr + (r)) macro
/Zephyr-latest/drivers/counter/
Dcounter_nxp_s32_sys_timer.c47 #define REG_READ(r) sys_read32(config->base + (r)) macro
119 const uint32_t now = REG_READ(STM_CNT); in stm_set_alarm()
155 diff = ticks_sub(ticks - 1, REG_READ(STM_CNT), top_val); in stm_set_alarm()
187 pending = FIELD_GET(STM_CCR_CEN_MASK, REG_READ(STM_CCR(channel))) && in stm_isr()
188 FIELD_GET(STM_CIR_CIF_MASK, REG_READ(STM_CIR(channel))); in stm_isr()
200 cb(dev, channel, REG_READ(STM_CNT), cb_args); in stm_isr()
211 REG_WRITE(STM_CR, REG_READ(STM_CR) | STM_CR_TEN(1U)); in nxp_s32_sys_timer_start()
220 REG_WRITE(STM_CR, REG_READ(STM_CR) & ~STM_CR_TEN_MASK); in nxp_s32_sys_timer_stop()
229 *ticks = REG_READ(STM_CNT); in nxp_s32_sys_timer_get_value()
275 if (REG_READ(STM_CIR(i)) & STM_CIR_CIF_MASK) { in nxp_s32_sys_timer_get_pending_int()
Dcounter_esp32_rtc.c230 uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG); in counter_esp32_isr()
/Zephyr-latest/soc/nxp/s32/s32k3/
Dpmc.c90 #define REG_READ(r) sys_read32((mem_addr_t)(DT_INST_REG_ADDR(0) + (r))) macro
116 if (!WAIT_FOR(FIELD_GET(PMC_LVSC_LVD15S_MASK, REG_READ(PMC_LVSC)) == 0U, in pmc_init()
121 REG_WRITE(PMC_CONFIG, REG_READ(PMC_CONFIG) | PMC_CONFIG_LMEN(1U)); in pmc_init()
126 if (!WAIT_FOR(FIELD_GET(PMC_CONFIG_LMSTAT_MASK, REG_READ(PMC_CONFIG)) == 1U, in pmc_init()
/Zephyr-latest/drivers/entropy/
Dentropy_esp32.c44 return REG_READ(WDEV_RND_REG); in entropy_esp32_get_u32()
/Zephyr-latest/drivers/input/
Dinput_esp32_touch_sensor.c141 uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG);