1 /*
2  * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <soc/rtc_cntl_reg.h>
8 #include <soc/timer_group_reg.h>
9 #include <soc/ext_mem_defs.h>
10 #include <soc/gpio_reg.h>
11 #include <soc/syscon_reg.h>
12 #include <soc/system_reg.h>
13 #include <riscv/interrupt.h>
14 #include <soc/interrupt_reg.h>
15 #include <soc/periph_defs.h>
16 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
17 
18 #include <zephyr/kernel_structs.h>
19 #include <string.h>
20 #include <zephyr/toolchain.h>
21 #include <soc.h>
22 #include <zephyr/arch/riscv/arch.h>
23 
24 #define ESP32C2_INTSTATUS_SLOT1_THRESHOLD	32
25 
arch_irq_enable(unsigned int irq)26 void arch_irq_enable(unsigned int irq)
27 {
28 	esp_intr_enable(irq);
29 }
30 
arch_irq_disable(unsigned int irq)31 void arch_irq_disable(unsigned int irq)
32 {
33 	esp_intr_disable(irq);
34 }
35 
arch_irq_is_enabled(unsigned int irq)36 int arch_irq_is_enabled(unsigned int irq)
37 {
38 	bool res = false;
39 	uint32_t key = irq_lock();
40 
41 	if (irq < 32) {
42 		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
43 	} else {
44 		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
45 	}
46 
47 	irq_unlock(key);
48 
49 	return res;
50 }
51 
soc_intr_get_next_source(void)52 uint32_t soc_intr_get_next_source(void)
53 {
54 	uint32_t status;
55 	uint32_t source;
56 
57 	status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) &
58 		esp_intr_get_enabled_intmask(0);
59 
60 	if (status) {
61 		source = __builtin_ffs(status) - 1;
62 	} else {
63 		status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) &
64 			esp_intr_get_enabled_intmask(1);
65 		source = (__builtin_ffs(status) - 1 + ESP32C2_INTSTATUS_SLOT1_THRESHOLD);
66 	}
67 
68 	return source;
69 }
70