Lines Matching refs:REG_READ
39 #define REG_READ(r) sys_read32(config->base + (r)) macro
77 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask); in eirq_nxp_s32_interrupt_handler()
129 reg_val = REG_READ(SIUL2_IREER0); in eirq_nxp_s32_enable_interrupt()
137 reg_val = REG_READ(SIUL2_IFEER0); in eirq_nxp_s32_enable_interrupt()
146 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
147 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq)); in eirq_nxp_s32_enable_interrupt()
157 REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
158 REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
161 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq)); in eirq_nxp_s32_disable_interrupt()
162 REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq)); in eirq_nxp_s32_disable_interrupt()
169 return REG_READ(SIUL2_DISR0) & REG_READ(SIUL2_DIRER0); in eirq_nxp_s32_get_pending()
199 REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) | BIT(irq)); in eirq_nxp_s32_init()
201 REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) & ~BIT(irq)); in eirq_nxp_s32_init()