| /Zephyr-latest/include/zephyr/linker/ |
| D | linker-devnull.h | 24 #if (!defined(RAM_ADDR) && !defined(RAM_BASE)) || !defined(RAM_SIZE)
55 #define DEVNULL_ADDR (RAM_ADDR + RAM_SIZE)
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| /Zephyr-latest/tests/drivers/memc/ram/src/ |
| D | main.c | 52 #define RAM_SIZE DT_REG_SIZE(DT_NODELABEL(ram0)) macro
70 test_ram_rw(buf_ram0, RAM_SIZE); in ZTEST()
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| /Zephyr-latest/cmake/linker_script/arm/ |
| D | linker.cmake | 32 math(EXPR RAM_SIZE "(${CONFIG_SRAM_SIZE} + 0) * 1024" OUTPUT_FORMAT HEXADECIMAL)
33 math(EXPR IDT_ADDR "${RAM_ADDR} + ${RAM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
41 zephyr_linker_memory(NAME RAM FLAGS wx START ${RAM_ADDR} SIZE ${RAM_SIZE})
148 zephyr_linker_symbol(SYMBOL __kernel_ram_end EXPR "(${RAM_ADDR} + ${RAM_SIZE})")
151 zephyr_linker_symbol(SYMBOL ARM_LIB_STACKHEAP EXPR "(${RAM_ADDR} + ${RAM_SIZE})" SIZE -0x1000)
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/ |
| D | adsp_memory.h | 22 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) macro
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| /Zephyr-latest/include/zephyr/arch/arm64/scripts/ |
| D | linker.ld | 47 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
69 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
289 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ |
| D | adsp_memory.h | 28 #define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE) macro
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | linker.ld | 37 #define RAM_SIZE 0x200000 macro
45 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE /* 2097kb */
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| /Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/scripts/ |
| D | linker.ld | 55 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
89 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
351 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | linker.ld | 59 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
75 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
|
| /Zephyr-latest/soc/infineon/cat1b/cyw20829/ |
| D | linker.ld | 48 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
79 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
379 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
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| /Zephyr-latest/soc/nuvoton/npcx/common/ecst/ |
| D | ecst_args.py | 64 RAM_SIZE = 0x01 variable
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| /Zephyr-latest/include/zephyr/arch/arm/cortex_m/scripts/ |
| D | linker.ld | 55 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K) macro
89 RAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
499 __kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
| /Zephyr-latest/soc/andestech/ae350/ |
| D | linker.ld | 57 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
80 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 122 len = RAM_SIZE
126 len = RAM_SIZE
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| /Zephyr-latest/include/zephyr/arch/riscv/common/ |
| D | linker.ld | 86 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
111 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | linker.ld | 50 #define RAM_SIZE KB(CONFIG_SRAM_SIZE) macro
75 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | ace-link.ld | 137 len = RAM_SIZE
141 len = RAM_SIZE
|
