Searched refs:RAM_BASE (Results 1 – 13 of 13) sorted by relevance
| /Zephyr-latest/include/zephyr/linker/ |
| D | linker-devnull.h | 24 #if (!defined(RAM_ADDR) && !defined(RAM_BASE)) || !defined(RAM_SIZE)
33 #define RAM_ADDR RAM_BASE
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | ilm.c | 45 #define RAM_BASE CONFIG_SRAM_BASE_ADDRESS macro
82 if ((uintptr_t)ram_addr < RAM_BASE) { in it8xxx2_configure_ilm_block()
85 const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE; in it8xxx2_configure_ilm_block()
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| D | linker.ld | 49 #define RAM_BASE CONFIG_SRAM_BASE_ADDRESS macro
75 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
312 . = RAM_BASE;
331 ASSERT((__sha256_ram_block_end < (RAM_BASE + 0x1000)), \
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| /Zephyr-latest/soc/intel/intel_adsp/common/ |
| D | rimage_modules.c | 39 .entry_point = RAM_BASE,
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| /Zephyr-latest/soc/andestech/ae350/common_linker/ |
| D | ram_start_nonzero.ld | 8 * Workaround for RAM_BASE is zero in XIP system, kernel object
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/ |
| D | adsp_memory.h | 21 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE) macro
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ |
| D | adsp_memory.h | 27 #define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE) macro
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | linker.ld | 36 #define RAM_BASE 0x1C070000 macro
45 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE /* 2097kb */
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | linker.ld | 58 #define RAM_BASE CONFIG_SRAM_BASE_ADDRESS macro
75 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | linker.ld | 56 #define RAM_BASE CONFIG_SRAM_BASE_ADDRESS macro
80 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
206 . = RAM_BASE;
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| /Zephyr-latest/include/zephyr/arch/riscv/common/ |
| D | linker.ld | 85 #define RAM_BASE CONFIG_SRAM_BASE_ADDRESS macro
111 RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
249 . = RAM_BASE;
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | ace-link.ld | 130 len = RAM_BASE - (DOUBLEEXC_VECTOR_PADDR_SRAM + MEM_VECT_TEXT_SIZE)
136 org = RAM_BASE,
140 org = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 121 org = RAM_BASE,
125 org = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION),
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