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Searched refs:MU_BASE (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
Dmemory.h88 #define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR macro
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/
Dmemory.h92 #define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR macro
/Zephyr-latest/soc/nxp/imx/imx8/adsp/
Dmemory.h92 #define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR macro
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dmemory.h97 #define MU_BASE XSHAL_MU2_SIDEB_BYPASS_PADDR macro
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dsoc.c50 #define MU_BASE (MU_Type *)DT_REG_ADDR(DT_INST(0, nxp_imx_mu)) macro
742 MU_SetFlags(MU_BASE, BOOT_FLAG); in imxrt_init()
803 while (MU_GetFlags(MU_BASE) != BOOT_FLAG) { in second_core_boot()