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Searched refs:L3_MEM_BASE_ADDR (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1))) macro
47 #define IMR_BOOT_LDR_MANIFEST_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_MANIFEST_OFFSET)
60 #define IMR_BOOT_LDR_DATA_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_DATA_OFFSET)
64 #define IMR_BOOT_LDR_BSS_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_BSS_OFFSET)
75 (IMR_L3_HEAP_BASE - L3_MEM_BASE_ADDR))
Dadsp_imr_layout.h16 #define IMR_LAYOUT_ADDRESS (L3_MEM_BASE_ADDR + IMR_LAYOUT_OFFSET)
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h33 #define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1))) macro
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower.c156 L3_MEM_BASE_ADDR); in pm_state_set()