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Searched refs:DT_INST_PHA (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/drivers/serial/
Duart_pl011_ambiq.h175 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
177 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
193 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
195 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
196 while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
197 DT_INST_PHA(n, ambiq_pwrcfg, mask)) { \
Duart_ns16550.c1938 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(\
/Zephyr-latest/drivers/spi/
Dspi_ambiq_bleif.c203 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
204 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
Dspi_ambiq_spid.c402 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
403 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
Dspi_ambiq_spic.c497 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
498 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
/Zephyr-latest/drivers/clock_control/
Dclock_control_nrf_auxpll.c131 DT_INST_PHA(n, nordic_ficrs, offset), \
/Zephyr-latest/drivers/adc/
Dadc_ambiq.c410 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
411 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
/Zephyr-latest/drivers/i2c/
Di2c_ambiq.c428 DT_INST_PHA(n, ambiq_pwrcfg, offset); \
429 sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
/Zephyr-latest/drivers/gpio/
Dgpio_lpc11u6x.c504 .clock_subsys = (clock_control_subsys_t) DT_INST_PHA(0, clocks, clkid),
/Zephyr-latest/include/zephyr/
Ddevicetree.h4329 #define DT_INST_PHA(inst, pha, cell) DT_INST_PHA_BY_IDX(inst, pha, 0, cell) macro
/Zephyr-latest/tests/lib/devicetree/api/src/
Dmain.c1119 zassert_equal(DT_INST_PHA(0, gpios, pin), 10, ""); in ZTEST()
1120 zassert_equal(DT_INST_PHA(0, gpios, flags), 20, ""); in ZTEST()