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Searched refs:DT_CLOCKS_CTLR (Results 1 – 25 of 34) sorted by relevance

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/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h26 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(fsrco)) \
28 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfrcodpll)) \
30 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfxo)) \
32 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(clkin0)) \
54 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
56 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcodpllrt)) \
59 DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), \
67 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hclk)) \
69 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcoem23)) \
86 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), DT_NODELABEL(hfrcodpll)) \
[all …]
Dsl_clock_manager_oscillator_config.h53 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(hfxo)) \
55 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(lfxo)) \
57 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(clkin0)) \
/Zephyr-latest/drivers/clock_control/
Dclock_control_mcux_scg.c129 #if DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(slow_clk)) in mcux_scg_init()
131 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sosc_clk)) in mcux_scg_init()
133 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sirc_clk)) in mcux_scg_init()
135 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(firc_clk)) in mcux_scg_init()
137 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk)) in mcux_scg_init()
Dclock_control_renesas_ra_cgc.c95 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \
96 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \
Dclock_control_wch_rcc.c23 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
32 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c39 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
51 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sosc_clk))
53 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
55 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
57 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
137 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(pll)), SCG_CLOCK_NODE(sosc_clk))
139 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(pll)), SCG_CLOCK_NODE(firc_clk))
/Zephyr-latest/drivers/entropy/
Dentropy_esp32.c71 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(trng0))); in entropy_esp32_init()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c42 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
44 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
/Zephyr-latest/tests/drivers/clock_control/pwm_clock/src/
Dmain.c15 static const struct device *clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(NODELABEL));
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h146 #define DT_CLOCKS_CTLR(node_id) DT_CLOCKS_CTLR_BY_IDX(node_id, 0) macro
/Zephyr-latest/samples/boards/nordic/clock_control/src/
Dmain.c13 #define SAMPLE_CLOCK_NODE DT_CLOCKS_CTLR(DT_ALIAS(sample_device))
/Zephyr-latest/soc/nordic/nrf92/
Dsoc.c73 DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); in trim_hsfll()
/Zephyr-latest/soc/nordic/nrf54h/
Dsoc.c102 DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); in trim_hsfll()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dadi_max32_clock_control.h53 #define DT_GCR_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(gcr))
Dstm32_clock_control.h121 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
258 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
283 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
299 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
/Zephyr-latest/drivers/mdio/
Dmdio_esp32.c103 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(mdio))); in mdio_esp32_initialize()
Dmdio_nxp_enet.c251 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(inst))), \
/Zephyr-latest/drivers/pwm/
Dpwm_max32.c132 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(_num))), \
Dpwm_nxp_flexio.c324 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
Dpwm_nrfx.c392 (DT_PROP(DT_CLOCKS_CTLR(PWM(idx)), clock_frequency)), \
/Zephyr-latest/drivers/ethernet/nxp_enet/
Deth_nxp_enet.c1001 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
1079 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(n))), \
1100 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(n))), \
/Zephyr-latest/drivers/counter/
Dcounter_max32_timer.c331 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(TIMER(_num))), \
Dcounter_mcux_qtmr.c309 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
/Zephyr-latest/drivers/ethernet/
Deth_esp32.c242 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(eth))); in eth_esp32_initialize()
/Zephyr-latest/drivers/usb/udc/
Dudc_renesas_ra.c507 uint32_t uclk_src = RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk))); in udc_renesas_ra_init()
509 uint32_t u60clk_src = RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u60clk))); in udc_renesas_ra_init()

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