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Searched refs:DT_CLOCKS_CTLR (Results 1 – 25 of 36) sorted by relevance

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/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h26 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(fsrco)) \
28 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfrcodpll)) \
30 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfxo)) \
32 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(clkin0)) \
54 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
56 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcodpllrt)) \
59 DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), \
67 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hclk)) \
69 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcoem23)) \
86 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(em01grpaclk)), DT_NODELABEL(hfrcodpll)) \
[all …]
Dsl_clock_manager_oscillator_config.h53 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(hfxo)) \
55 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(lfxo)) \
57 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(hfrcodpll)), DT_NODELABEL(clkin0)) \
/Zephyr-latest/drivers/clock_control/
Dclock_control_mcux_scg.c129 #if DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(slow_clk)) in mcux_scg_init()
131 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sosc_clk)) in mcux_scg_init()
133 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(sirc_clk)) in mcux_scg_init()
135 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(firc_clk)) in mcux_scg_init()
137 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk)) in mcux_scg_init()
Dclock_control_renesas_ra_cgc.c109 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \
110 (RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \
Dclock_control_wch_rcc.c25 #if DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hse_clock)
27 #elif DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hsi_clock)
Dclock_control_nrf2_hsfll.c225 static const struct device *hsfll_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(cpu))); in dvfs_low_init()
/Zephyr-latest/soc/nordic/common/
Dsoc_nrf_common.h253 (COND_CODE_1(DT_NODE_HAS_PROP(DT_CLOCKS_CTLR(node), clock_frequency), \
254 (DT_PROP(DT_CLOCKS_CTLR(node), clock_frequency)), \
255 (DT_PROP_LAST(DT_CLOCKS_CTLR(node), supported_clock_frequency)))), \
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c39 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
51 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sosc_clk))
53 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
55 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
57 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
137 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(pll)), SCG_CLOCK_NODE(sosc_clk))
139 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(pll)), SCG_CLOCK_NODE(firc_clk))
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c42 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
44 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
/Zephyr-latest/tests/drivers/clock_control/pwm_clock/src/
Dmain.c15 static const struct device *clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(NODELABEL));
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h146 #define DT_CLOCKS_CTLR(node_id) DT_CLOCKS_CTLR_BY_IDX(node_id, 0) macro
/Zephyr-latest/samples/boards/nordic/clock_control/src/
Dmain.c13 #define SAMPLE_CLOCK_NODE DT_CLOCKS_CTLR(DT_ALIAS(sample_device))
/Zephyr-latest/drivers/entropy/
Dentropy_esp32.c102 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(trng0))); in entropy_esp32_init()
/Zephyr-latest/soc/nordic/nrf92/
Dsoc.c73 DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); in trim_hsfll()
/Zephyr-latest/soc/nordic/nrf54h/
Dsoc.c103 DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); in trim_hsfll()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dadi_max32_clock_control.h53 #define DT_GCR_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(gcr))
Dstm32_clock_control.h124 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
296 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
321 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
340 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
359 #define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
/Zephyr-latest/drivers/mdio/
Dmdio_esp32.c103 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(mdio))); in mdio_esp32_initialize()
Dmdio_nxp_enet.c251 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(inst))), \
/Zephyr-latest/drivers/pwm/
Dpwm_max32.c132 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(_num))), \
Dpwm_nrfx.c524 (DT_PROP(DT_CLOCKS_CTLR(PWM(idx)), clock_frequency)), \
530 ? DEVICE_DT_GET(DT_CLOCKS_CTLR(PWM(idx))) \
Dpwm_nxp_flexio.c324 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
/Zephyr-latest/drivers/watchdog/
Dwdt_renesas_ra.c316 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(id)), \
/Zephyr-latest/drivers/ethernet/
Deth_nxp_enet.c998 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
1076 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(n))), \
1097 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(n))), \
/Zephyr-latest/drivers/counter/
Dcounter_max32_timer.c331 .clock = DEVICE_DT_GET(DT_CLOCKS_CTLR(TIMER(_num))), \

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