Searched refs:ADC_SEL (Results 1 – 16 of 16) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32c0_clock.h | 74 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) macro
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| D | stm32wb_clock.h | 88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) macro
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| D | stm32wl_clock.h | 87 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) macro
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| D | stm32u0_clock.h | 88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) macro
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| D | stm32wba_clock.h | 100 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) macro
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| D | stm32g0_clock.h | 88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) macro
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| D | stm32l4_clock.h | 94 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) macro
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| D | stm32h7rs_clock.h | 106 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG) macro
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| D | stm32h7_clock.h | 132 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG) macro
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 81 <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 100 <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;
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| /Zephyr-latest/boards/st/stm32u083c_dk/ |
| D | stm32u083c_dk.dts | 80 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
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| /Zephyr-latest/boards/st/nucleo_u083rc/ |
| D | nucleo_u083rc.dts | 120 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
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| /Zephyr-latest/boards/st/nucleo_g071rb/ |
| D | nucleo_g071rb.dts | 147 <&rcc STM32_SRC_SYSCLK ADC_SEL(0)>;
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| /Zephyr-latest/dts/arm/st/wba/ |
| D | stm32wba.dtsi | 417 <&rcc STM32_SRC_HCLK1 ADC_SEL(0)>;
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| /Zephyr-latest/doc/releases/ |
| D | migration-guide-3.5.rst | 210 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
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