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Searched refs:pclken (Results 1 – 25 of 74) sorted by relevance

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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_mp1.c20 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
24 switch (pclken->bus) { in stm32_clock_control_on()
26 LL_APB1_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
29 LL_APB2_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
32 LL_APB3_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
35 LL_APB4_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
38 LL_APB5_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
41 LL_AHB2_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
44 LL_AHB3_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
47 LL_AHB4_GRP1_EnableClock(pclken->enr); in stm32_clock_control_on()
[all …]
Dclock_stm32_mco.c27 const struct stm32_pclken pclken[1]; member
33 const struct stm32_pclken *pclken = &config->pclken[0]; in stm32_mco_init() local
36 err = enabled_clock(pclken->bus); in stm32_mco_init()
44 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), in stm32_mco_init()
45 STM32_MCO_CFGR_MASK_GET(pclken->enr) << in stm32_mco_init()
46 STM32_MCO_CFGR_SHIFT_GET(pclken->enr)); in stm32_mco_init()
48 DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), in stm32_mco_init()
49 STM32_MCO_CFGR_VAL_GET(pclken->enr) << in stm32_mco_init()
50 STM32_MCO_CFGR_SHIFT_GET(pclken->enr)); in stm32_mco_init()
73 .pclken = STM32_DT_INST_CLOCKS(inst), \
Dclock_stm32_ll_wb0.c212 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
213 const mem_addr_t reg = RCC_REG(pclken->bus); in stm32_clock_control_on()
217 if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) { in stm32_clock_control_on()
222 sys_set_bits(reg, pclken->enr); in stm32_clock_control_on()
236 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_off() local
237 const mem_addr_t reg = RCC_REG(pclken->bus); in stm32_clock_control_off()
240 if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) { in stm32_clock_control_off()
245 sys_clear_bits(reg, pclken->enr); in stm32_clock_control_off()
254 struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system; in stm32_clock_control_configure() local
255 const uint32_t shift = STM32_CLOCK_SHIFT_GET(pclken->enr); in stm32_clock_control_configure()
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Dclock_stm32_ll_wba.c68 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
81 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
90 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_off() local
94 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
100 pclken->enr); in stm32_clock_control_off()
111 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_configure() local
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Dclock_stm32_ll_common.c255 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
260 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
265 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
266 pclken->enr); in stm32_clock_control_on()
270 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
279 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_off() local
283 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
288 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
289 pclken->enr); in stm32_clock_control_off()
300 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_configure() local
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Dclock_stm32_ll_u5.c156 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
161 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
166 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
167 pclken->enr); in stm32_clock_control_on()
169 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
178 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_off() local
182 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
187 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
188 pclken->enr); in stm32_clock_control_off()
197 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_configure() local
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Dclock_stm32_mux.c21 const struct stm32_pclken pclken; member
29 (clock_control_subsys_t) &cfg->pclken, NULL) != 0) { in stm32_clk_mux_init()
40 .pclken = STM32_CLOCK_INFO(0, DT_DRV_INST(id)) \
Dclock_stm32_ll_h5.c150 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_on() local
155 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
160 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
161 pclken->enr); in stm32_clock_control_on()
163 temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus); in stm32_clock_control_on()
172 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_off() local
176 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
181 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
182 pclken->enr); in stm32_clock_control_off()
191 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); in stm32_clock_control_configure() local
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Dclock_stm32_ll_h7.c387 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); local
392 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
399 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
403 temp = sys_read32(STM32H7_BUS_CLK_REG + pclken->bus);
414 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); local
418 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
425 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
436 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); local
442 err = enabled_clock(pclken->bus);
450 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_sdmmc.c31 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(sdmmc1)); in ZTEST() local
39 (clock_control_subsys_t) &pclken[0]); in ZTEST()
47 if (pclken[1].bus == STM32_SRC_CK48) { in ZTEST()
51 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
54 (clock_control_subsys_t) &pclken[1], in ZTEST()
66 if (pclken[1].bus == STM32_SRC_CK48) { in ZTEST()
70 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
79 if (pclken[1].bus == STM32_SRC_CK48) { in ZTEST()
103 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
113 (clock_control_subsys_t) &pclken[1], in ZTEST()
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Dtest_stm32_clock_configuration_lptim.c26 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(lptim1)); in ZTEST() local
34 (clock_control_subsys_t) &pclken[0]); in ZTEST()
43 (clock_control_subsys_t) &pclken[1], in ZTEST()
51 if (pclken[1].bus == STM32_SRC_LSE) { in ZTEST()
55 } else if (pclken[1].bus == STM32_SRC_LSI) { in ZTEST()
65 (clock_control_subsys_t) &pclken[1], in ZTEST()
81 (clock_control_subsys_t) &pclken[0], in ZTEST()
95 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_adc.c59 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1)); in ZTEST() local
67 (clock_control_subsys_t)&pclken[0]); in ZTEST()
73 (clock_control_subsys_t) &pclken[0]); in ZTEST()
79 (clock_control_subsys_t)&pclken[0]); in ZTEST()
87 (clock_control_subsys_t) &pclken[1], in ZTEST()
96 switch (pclken[1].bus) { in ZTEST()
117 (clock_control_subsys_t)&pclken[1]); in ZTEST()
122 (clock_control_subsys_t) &pclken[1], in ZTEST()
142 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_i2s.c21 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2s2)); in ZTEST() local
29 (clock_control_subsys_t) &pclken[0]); in ZTEST()
39 (clock_control_subsys_t) &pclken[1], in ZTEST()
47 if (pclken[1].bus == STM32_SRC_PLLI2S_R) { in ZTEST()
57 (clock_control_subsys_t) &pclken[1], in ZTEST()
70 (clock_control_subsys_t) &pclken[0]); in ZTEST()
Dtest_stm32_clock_configuration_i2c.c76 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2c1)); in ZTEST() local
83 (clock_control_subsys_t)&pclken[0]); in ZTEST()
89 (clock_control_subsys_t) &pclken[0]); in ZTEST()
95 (clock_control_subsys_t)&pclken[0]); in ZTEST()
105 i2c_set_clock(&pclken[2]); in ZTEST()
107 i2c_set_clock(&pclken[1]); in ZTEST()
114 (clock_control_subsys_t) &pclken[0], in ZTEST()
128 (clock_control_subsys_t) &pclken[0]); in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST() local
46 (clock_control_subsys_t) &pclken[0]); in ZTEST()
55 (clock_control_subsys_t) &pclken[1], in ZTEST()
63 if (pclken[1].bus == STM32_SRC_HSI16) { in ZTEST()
67 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
77 (clock_control_subsys_t) &pclken[1], in ZTEST()
90 (clock_control_subsys_t) &pclken[0], in ZTEST()
102 (clock_control_subsys_t) &pclken[0]); in ZTEST()
/Zephyr-latest/drivers/memc/
Dmemc_stm32.c34 const struct stm32_pclken *pclken; member
61 r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]); in memc_stm32_init()
69 r = clock_control_configure(clk, (clock_control_subsys_t)&config->pclken[1], NULL); in memc_stm32_init()
91 static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0); variable
95 .pclken = pclken,
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c38 static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); in ZTEST() local
39 struct stm32_pclken spi1_reg_clk_cfg = pclken[0]; in ZTEST()
54 struct stm32_pclken spi1_domain_clk_cfg = pclken[1]; in ZTEST()
65 if (pclken[1].bus == STM32_SRC_PLL1_Q) { in ZTEST()
69 } else if (pclken[1].bus == STM32_SRC_PLL2_P) { in ZTEST()
73 } else if (pclken[1].bus == STM32_SRC_PLL3_P) { in ZTEST()
77 } else if (pclken[1].bus == STM32_SRC_CKPER) { in ZTEST()
108 zassert_true(0, "Unexpected domain_clk src(0x%x)", pclken[1].bus); in ZTEST()
/Zephyr-latest/drivers/usb/device/
Dusb_dc_dw_stm32.h18 const struct stm32_pclken *const pclken; member
34 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
41 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
52 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in clk_enable_st_stm32f4_fsotg()
67 .pclken = pclken_##n, \
/Zephyr-latest/soc/st/stm32/common/
Dstm32_backup_sram.c18 struct stm32_pclken pclken; member
35 ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken); in stm32_backup_sram_init()
57 .pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
/Zephyr-latest/drivers/sensor/st/stm32_digi_temp/
Dstm32_digi_temp.c45 struct stm32_pclken pclken; member
178 if (clock_control_on(clk, (clock_control_subsys_t) &cfg->pclken) != 0) { in stm32_digi_temp_init()
186 if (clock_control_get_rate(clk, (clock_control_subsys_t) &cfg->pclken, in stm32_digi_temp_init()
234 err = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken); in stm32_digi_temp_pm_action()
246 err = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken); in stm32_digi_temp_pm_action()
278 .pclken = { \
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h24 const struct stm32_pclken *const pclken; member
42 (void *)&clk->pclken[1], in stm32f4_fsotg_enable_clk()
49 (void *)&clk->pclken[1], in stm32f4_fsotg_enable_clk()
60 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in stm32f4_fsotg_enable_clk()
88 .pclken = pclken_##n, \
/Zephyr-latest/soc/st/stm32/stm32wbax/hci_if/
Dbleplat.c30 struct stm32_pclken *pclken; member
97 rng_pclken = (clock_control_subsys_t)&dev_cfg->pclken[0]; in enable_rng_clock()
/Zephyr-latest/drivers/can/
Dcan_stm32h7_fdcan.c40 const struct stm32_pclken *pclken; member
122 (clock_control_subsys_t)&stm32h7_cfg->pclken[1], in can_stm32h7_clock_enable()
135 (clock_control_subsys_t)&stm32h7_cfg->pclken[1], &fdcan_clock); in can_stm32h7_clock_enable()
148 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken[0]); in can_stm32h7_clock_enable()
261 .pclken = can_stm32h7_pclken_##n, \
/Zephyr-latest/drivers/sensor/st/qdec_stm32/
Dqdec_stm32.c31 struct stm32_pclken pclken; member
97 (clock_control_subsys_t)&dev_cfg->pclken); in qdec_stm32_initialize()
152 .pclken = {.bus = DT_CLOCKS_CELL(DT_INST_PARENT(n), bus), \
/Zephyr-latest/drivers/ipm/
Dipm_stm32_hsem.c37 struct stm32_pclken pclken; member
168 if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) { in stm32_hsem_mailbox_init()
197 .pclken = {

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