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Searched refs:clk_div (Results 1 – 24 of 24) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_ast10x0.c99 uint32_t reg, src, clk_div; in aspeed_clock_control_get_rate() local
112 clk_div = I3C_CLK_DIV_REG_TO_VAL(FIELD_GET(I3C_CLK_DIV_SEL, reg)); in aspeed_clock_control_get_rate()
113 *rate = src / clk_div; in aspeed_clock_control_get_rate()
118 clk_div = HCLK_DIV_REG_TO_VAL(FIELD_GET(HCLK_DIV_SEL, reg)); in aspeed_clock_control_get_rate()
119 *rate = src / clk_div; in aspeed_clock_control_get_rate()
124 clk_div = PCLK_DIV_REG_TO_VAL(FIELD_GET(PCLK_DIV_SEL, reg)); in aspeed_clock_control_get_rate()
125 *rate = src / clk_div; in aspeed_clock_control_get_rate()
Dclock_control_numaker_scc.c88 scc_subsys->pcc.clk_div); in numaker_scc_configure()
/Zephyr-Core-3.7.0/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi86 clk_div = <RA_SYS_CLOCK_DIV_1>;
93 clk_div = <RA_SYS_CLOCK_DIV_2>;
100 clk_div = <RA_SYS_CLOCK_DIV_4>;
107 clk_div = <RA_SYS_CLOCK_DIV_8>;
114 clk_div = <RA_SYS_CLOCK_DIV_8>;
121 clk_div = <RA_SYS_CLOCK_DIV_4>;
128 clk_div = <RA_SYS_CLOCK_DIV_2>;
135 clk_div = <RA_SYS_CLOCK_DIV_4>;
148 clk_div = <RA_SYS_CLOCK_DIV_8>;
/Zephyr-Core-3.7.0/drivers/watchdog/
Dwdt_wwdt_numaker.c30 uint32_t clk_div; member
47 *rate = __LIRC / (cfg->clk_div + 1); in m_wwdt_numaker_clk_get_rate()
51 *rate = CLK_GetHCLKFreq() / 2048 / (cfg->clk_div + 1); in m_wwdt_numaker_clk_get_rate()
262 scc_subsys.pcc.clk_div = cfg->clk_div; in wwdt_numaker_init()
292 .clk_div = DT_INST_CLOCKS_CELL(0, clock_divider),
/Zephyr-Core-3.7.0/include/zephyr/drivers/clock_control/
Dclock_control_numaker.h36 uint32_t clk_div; member
/Zephyr-Core-3.7.0/drivers/can/
Dcan_numaker.c39 uint32_t clk_div; member
91 scc_subsys.pcc.clk_div = config->clk_div; in can_numaker_init_unlocked()
272 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
/Zephyr-Core-3.7.0/drivers/spi/
Dspi_numaker.c31 uint32_t clk_div; member
302 scc_subsys.pcc.clk_div = dev_cfg->clk_div; in spi_numaker_init()
355 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
/Zephyr-Core-3.7.0/drivers/sensor/st/stm32_digi_temp/
Dstm32_digi_temp.c116 int clk_div; in stm32_digi_temp_configure() local
121 clk_div = MIN(DIV_ROUND_UP(data->pclk_freq, ONE_MHZ), 127); in stm32_digi_temp_configure()
123 clk_div << DTS_CFGR1_HSREF_CLK_DIV_Pos); in stm32_digi_temp_configure()
/Zephyr-Core-3.7.0/drivers/mipi_dbi/
Dmipi_dbi_smartbond.c397 uint8_t clk_div = in mipi_dbi_smartbond_configure() local
406 (clk_div >= 2 ? clk_div / 2 : clk_div)); in mipi_dbi_smartbond_configure()
/Zephyr-Core-3.7.0/drivers/adc/
Dadc_numaker.c34 uint32_t clk_div; member
334 scc_subsys.pcc.clk_div = cfg->clk_div; in adc_numaker_init()
388 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
/Zephyr-Core-3.7.0/drivers/serial/
Duart_numaker.c26 uint32_t clk_div; member
201 scc_subsys.pcc.clk_div = config->clk_div; in uart_numaker_init()
434 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
Duart_b91.c47 uint16_t clk_div; member
207 uart->clk_div = divider; in uart_b91_init()
/Zephyr-Core-3.7.0/drivers/memc/
Dmemc_smartbond_nor_psram.c50 static void memc_set_status(bool status, int clk_div) in memc_set_status() argument
61 CLK_AMBA_REG_SET_FIELD(QSPI2_DIV, clk_amba_reg, clk_div); in memc_set_status()
/Zephyr-Core-3.7.0/drivers/sensor/espressif/esp32_temp/
Desp32_temp.c81 data->temp_sensor.dac_offset, data->temp_sensor.clk_div); in esp32_temp_init()
/Zephyr-Core-3.7.0/drivers/pwm/
Dpwm_numaker.c38 uint32_t clk_div; member
483 scc_subsys.pcc.clk_div = cfg->clk_div; in pwm_numaker_init()
567 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
/Zephyr-Core-3.7.0/drivers/ethernet/
Deth_numaker.c50 uint32_t clk_div; member
725 scc_subsys.pcc.clk_div = cfg->clk_div; in eth_numaker_init()
782 .clk_div = DT_INST_CLOCKS_CELL(0, clock_divider),
/Zephyr-Core-3.7.0/boards/renesas/ek_ra8m1/
Dek_ra8m1.dts94 clk_div = <RA_SCI_CLOCK_DIV_4>;
/Zephyr-Core-3.7.0/drivers/i2c/
Di2c_numaker.c62 uint32_t clk_div; member
698 scc_subsys.pcc.clk_div = config->clk_div; in i2c_numaker_init()
765 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
Di2c_ite_enhance.c298 uint32_t clk_div, psr, pll_clock, psr_h, psr_l; in i2c_enhanced_port_set_frequency() local
314 clk_div = (IT8XXX2_ECPM_SCDCR2 & 0x0F) + 1U; in i2c_enhanced_port_set_frequency()
316 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U; in i2c_enhanced_port_set_frequency()
/Zephyr-Core-3.7.0/drivers/i2s/
Di2s_sam_ssc.c516 uint32_t clk_div = SOC_ATMEL_SAM_MCK_FREQ_HZ / bit_clk_freq / 2U; in bit_clock_set() local
518 if (clk_div == 0U || clk_div >= (1 << 12)) { in bit_clock_set()
523 ssc->SSC_CMR = clk_div; in bit_clock_set()
/Zephyr-Core-3.7.0/drivers/display/
Ddisplay_renesas_lcdc.c140 uint8_t clk_div = in display_smartbond_configure() local
149 da1469x_lcdc_set_status(true, LCDC_SMARTBOND_IS_PLL_REQUIRED, clk_div); in display_smartbond_configure()
/Zephyr-Core-3.7.0/drivers/disk/
Dsdmmc_stm32.c770 #if DT_INST_NODE_HAS_PROP(0, clk_div)
771 .Init.ClockDiv = DT_INST_PROP(0, clk_div),
/Zephyr-Core-3.7.0/drivers/usb/device/
Dusb_dc_numaker.c76 uint32_t clk_div; member
366 scc_subsys.pcc.clk_div = config->clk_div; in numaker_usbd_hw_setup()
1982 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
/Zephyr-Core-3.7.0/drivers/usb_c/tcpc/
Ducpd_numaker.c2357 .pcc.clk_div = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, clock_divider), \