1 /*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "analog.h"
8 #include "clock.h"
9
10 #include <zephyr/device.h>
11 #include <zephyr/drivers/uart.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/irq.h>
14 #include <zephyr/drivers/interrupt_controller/riscv_plic.h>
15
16
17 /* Driver dts compatibility: telink,b91_uart */
18 #define DT_DRV_COMPAT telink_b91_uart
19
20 /* Get UART instance */
21 #define GET_UART(dev) ((volatile struct uart_b91_t *) \
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
23
24 /* UART TX buffer count max value */
25 #define UART_TX_BUF_CNT ((uint8_t)8u)
26
27 /* UART TX/RX data registers size */
28 #define UART_DATA_SIZE ((uint8_t)4u)
29
30 /* Parity type */
31 #define UART_PARITY_NONE ((uint8_t)0u)
32 #define UART_PARITY_EVEN ((uint8_t)1u)
33 #define UART_PARITY_ODD ((uint8_t)2u)
34
35 /* Stop bits length */
36 #define UART_STOP_BIT_1 ((uint8_t)0u)
37 #define UART_STOP_BIT_1P5 BIT(4)
38 #define UART_STOP_BIT_2 BIT(5)
39
40 /* TX RX reset bits */
41 #define UART_RX_RESET_BIT BIT(6)
42 #define UART_TX_RESET_BIT BIT(7)
43
44 /* B91 UART registers structure */
45 struct uart_b91_t {
46 uint8_t data_buf[UART_DATA_SIZE];
47 uint16_t clk_div;
48 uint8_t ctrl0;
49 uint8_t ctrl1;
50 uint8_t ctrl2;
51 uint8_t ctrl3;
52 uint16_t rxtimeout;
53 uint8_t bufcnt;
54 uint8_t status;
55 uint8_t txrx_status;
56 uint8_t state;
57 };
58
59 /* B91 UART data structure */
60 struct uart_b91_data {
61 uint8_t tx_byte_index;
62 uint8_t rx_byte_index;
63 struct uart_config cfg;
64 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
65 uart_irq_callback_user_data_t callback;
66 void *cb_data;
67 #endif
68 };
69
70 /* B91 UART config structure */
71 struct uart_b91_config {
72 const struct pinctrl_dev_config *pcfg;
73 uint32_t uart_addr;
74 uint32_t baud_rate;
75 void (*pirq_connect)(void);
76 };
77
78 /* rxtimeout register enums */
79 enum {
80 UART_ERR_IRQ_MASK = BIT(15),
81 };
82
83 /* ctrl0 register enums */
84 enum {
85 UART_RX_IRQ_MASK = BIT(6),
86 UART_TX_IRQ_MASK = BIT(7),
87 };
88
89 /* ctrl3 register enums */
90 enum {
91 FLD_UART_RX_IRQ_TRIQ_LEV_OFFSET = 0,
92 FLD_UART_TX_IRQ_TRIQ_LEV_OFFSET = 4,
93 };
94
95 /* bufcnt register enums */
96 enum {
97 FLD_UART_RX_BUF_CNT_OFFSET = 0,
98 FLD_UART_TX_BUF_CNT_OFFSET = 4,
99 };
100
101 /* status register enums */
102 enum {
103 UART_IRQ_STATUS = BIT(3),
104 UART_RX_ERR_STATUS = BIT(7),
105 };
106
107
108 /* Get tx fifo count */
uart_b91_get_tx_bufcnt(volatile struct uart_b91_t * uart)109 static inline uint8_t uart_b91_get_tx_bufcnt(volatile struct uart_b91_t *uart)
110 {
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET;
112 }
113
114 /* Get rx fifo count */
uart_b91_get_rx_bufcnt(volatile struct uart_b91_t * uart)115 static inline uint8_t uart_b91_get_rx_bufcnt(volatile struct uart_b91_t *uart)
116 {
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET;
118 }
119
120 /* Check for prime */
uart_b91_is_prime(uint32_t n)121 static uint8_t uart_b91_is_prime(uint32_t n)
122 {
123 uint32_t i = 5;
124
125 if (n <= 3) {
126 return 1;
127 } else if ((n % 2 == 0) || (n % 3 == 0)) {
128 return 0;
129 }
130
131 for (i = 5; i * i < n; i += 6) {
132 if ((n % i == 0) || (n % (i + 2)) == 0) {
133 return 0;
134 }
135 }
136
137 return 1;
138 }
139
140 /* Calculate the best bit width */
uart_b91_cal_div_and_bwpc(uint32_t baudrate,uint32_t pclk,uint16_t * divider,uint8_t * bwpc)141 static void uart_b91_cal_div_and_bwpc(uint32_t baudrate, uint32_t pclk,
142 uint16_t *divider, uint8_t *bwpc)
143 {
144 uint8_t i = 0, j = 0;
145 uint32_t primeInt = 0;
146 uint8_t primeDec = 0;
147 uint32_t D_intdec[13], D_int[13];
148 uint8_t D_dec[13];
149
150 primeInt = pclk / baudrate;
151 primeDec = 10 * pclk / baudrate - 10 * primeInt;
152
153 if (uart_b91_is_prime(primeInt)) {
154 primeInt += 1;
155 } else if (primeDec > 5) {
156 primeInt += 1;
157 if (uart_b91_is_prime(primeInt)) {
158 primeInt -= 1;
159 }
160 }
161
162 for (i = 3; i <= 15; i++) {
163 D_intdec[i - 3] = (10 * primeInt) / (i + 1);
164 D_dec[i - 3] = D_intdec[i - 3] - 10 * (D_intdec[i - 3] / 10);
165 D_int[i - 3] = D_intdec[i - 3] / 10;
166 }
167
168 /* find the max and min one decimation point */
169 uint8_t position_min = 0, position_max = 0;
170 uint32_t min = 0xffffffff, max = 0x00;
171
172 for (j = 0; j < 13; j++) {
173 if ((D_dec[j] <= min) && (D_int[j] != 0x01)) {
174 min = D_dec[j];
175 position_min = j;
176 }
177 if (D_dec[j] >= max) {
178 max = D_dec[j];
179 position_max = j;
180 }
181 }
182
183 if ((D_dec[position_min] < 5) && (D_dec[position_max] >= 5)) {
184 if (D_dec[position_min] < (10 - D_dec[position_max])) {
185 *bwpc = position_min + 3;
186 *divider = D_int[position_min] - 1;
187 } else {
188 *bwpc = position_max + 3;
189 *divider = D_int[position_max];
190 }
191 } else if ((D_dec[position_min] < 5) && (D_dec[position_max] < 5)) {
192 *bwpc = position_min + 3;
193 *divider = D_int[position_min] - 1;
194 } else {
195 *bwpc = position_max + 3;
196 *divider = D_int[position_max];
197 }
198 }
199
200 /* Initializes the UART instance */
uart_b91_init(volatile struct uart_b91_t * uart,uint16_t divider,uint8_t bwpc,uint8_t parity,uint8_t stop_bit)201 static void uart_b91_init(volatile struct uart_b91_t *uart, uint16_t divider,
202 uint8_t bwpc, uint8_t parity, uint8_t stop_bit)
203 {
204 /* config clock */
205 divider = divider | FLD_UART_CLK_DIV_EN;
206 uart->ctrl0 = bwpc;
207 uart->clk_div = divider;
208
209 /* config parity */
210 if (parity) {
211 /* enable parity function */
212 uart->ctrl1 |= FLD_UART_PARITY_ENABLE;
213
214 if (parity == UART_PARITY_EVEN) {
215 /* enable even parity */
216 uart->ctrl1 &= (~FLD_UART_PARITY_POLARITY);
217 } else if (parity == UART_PARITY_ODD) {
218 /* enable odd parity */
219 uart->ctrl1 |= FLD_UART_PARITY_POLARITY;
220 }
221 } else {
222 uart->ctrl1 &= (~FLD_UART_PARITY_ENABLE); /* disable parity function */
223 }
224
225 /* stop bit config */
226 uart->ctrl1 &= (~FLD_UART_STOP_SEL);
227 uart->ctrl1 |= stop_bit;
228 }
229
230 /* API implementation: irq handler */
uart_b91_irq_handler(const struct device * dev)231 static void uart_b91_irq_handler(const struct device *dev)
232 {
233 #ifndef CONFIG_UART_INTERRUPT_DRIVEN
234 ARG_UNUSED(dev);
235 #else
236 struct uart_b91_data *data = dev->data;
237
238 if (data->callback != NULL) {
239 data->callback(dev, data->cb_data);
240 }
241 #endif
242 }
243
244 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
245 /* API implementation: configure */
uart_b91_configure(const struct device * dev,const struct uart_config * cfg)246 static int uart_b91_configure(const struct device *dev,
247 const struct uart_config *cfg)
248 {
249 struct uart_b91_data *data = dev->data;
250 uint16_t divider;
251 uint8_t bwpc;
252 uint8_t parity;
253 uint8_t stop_bits;
254
255 volatile struct uart_b91_t *uart = GET_UART(dev);
256
257 /* check parity */
258 if (cfg->parity == UART_CFG_PARITY_NONE) {
259 parity = UART_PARITY_NONE;
260 } else if (cfg->parity == UART_CFG_PARITY_ODD) {
261 parity = UART_PARITY_ODD;
262 } else if (cfg->parity == UART_CFG_PARITY_EVEN) {
263 parity = UART_PARITY_EVEN;
264 } else {
265 return -ENOTSUP;
266 }
267
268 /* check stop bits */
269 if (cfg->stop_bits == UART_CFG_STOP_BITS_1) {
270 stop_bits = UART_STOP_BIT_1;
271 } else if (cfg->stop_bits == UART_CFG_STOP_BITS_1_5) {
272 stop_bits = UART_STOP_BIT_1P5;
273 } else if (cfg->stop_bits == UART_CFG_STOP_BITS_2) {
274 stop_bits = UART_STOP_BIT_2;
275 } else {
276 return -ENOTSUP;
277 }
278
279 /* check flow control */
280 if (cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
281 return -ENOTSUP;
282 }
283
284 /* UART configure */
285 uart_b91_cal_div_and_bwpc(cfg->baudrate, sys_clk.pclk * 1000 * 1000, ÷r, &bwpc);
286 uart_b91_init(uart, divider, bwpc, parity, stop_bits);
287
288 /* save configuration */
289 data->cfg = *cfg;
290
291 return 0;
292 }
293
294 /* API implementation: config_get */
uart_b91_config_get(const struct device * dev,struct uart_config * cfg)295 static int uart_b91_config_get(const struct device *dev,
296 struct uart_config *cfg)
297 {
298 struct uart_b91_data *data = dev->data;
299
300 *cfg = data->cfg;
301
302 return 0;
303 }
304 #endif
305
306 /* API implementation: driver initialization */
uart_b91_driver_init(const struct device * dev)307 static int uart_b91_driver_init(const struct device *dev)
308 {
309 int status = 0;
310 uint16_t divider = 0u;
311 uint8_t bwpc = 0u;
312 volatile struct uart_b91_t *uart = GET_UART(dev);
313 const struct uart_b91_config *cfg = dev->config;
314 struct uart_b91_data *data = dev->data;
315
316 /* Reset Tx, Rx status before usage */
317 uart->status |= UART_RX_RESET_BIT | UART_TX_RESET_BIT;
318 data->rx_byte_index = 0;
319 data->tx_byte_index = 0;
320
321 /* configure pins */
322 status = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
323 if (status < 0) {
324 return status;
325 }
326
327 uart_b91_cal_div_and_bwpc(cfg->baud_rate, sys_clk.pclk * 1000 * 1000, ÷r, &bwpc);
328 uart_b91_init(uart, divider, bwpc, UART_PARITY_NONE, UART_STOP_BIT_1);
329
330 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
331 cfg->pirq_connect();
332 #endif
333
334 return 0;
335 }
336
337 /* API implementation: poll_out */
uart_b91_poll_out(const struct device * dev,uint8_t c)338 static void uart_b91_poll_out(const struct device *dev, uint8_t c)
339 {
340 volatile struct uart_b91_t *uart = GET_UART(dev);
341 struct uart_b91_data *data = dev->data;
342
343 while (uart_b91_get_tx_bufcnt(uart) >= UART_TX_BUF_CNT) {
344 };
345
346 uart->data_buf[data->tx_byte_index] = c;
347 data->tx_byte_index = (data->tx_byte_index + 1) % ARRAY_SIZE(uart->data_buf);
348 }
349
350 /* API implementation: poll_in */
uart_b91_poll_in(const struct device * dev,unsigned char * c)351 static int uart_b91_poll_in(const struct device *dev, unsigned char *c)
352 {
353 volatile struct uart_b91_t *uart = GET_UART(dev);
354 struct uart_b91_data *data = dev->data;
355
356 if (uart_b91_get_rx_bufcnt(uart) == 0) {
357 return -1;
358 }
359
360 *c = uart->data_buf[data->rx_byte_index];
361 data->rx_byte_index = (data->rx_byte_index + 1) % ARRAY_SIZE(uart->data_buf);
362
363 return 0;
364 }
365
366 /* API implementation: err_check */
uart_b91_err_check(const struct device * dev)367 static int uart_b91_err_check(const struct device *dev)
368 {
369 volatile struct uart_b91_t *uart = GET_UART(dev);
370
371 return ((uart->status & UART_RX_ERR_STATUS) != 0) ? 1 : 0;
372 }
373
374 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
375
376 /* API implementation: fifo_fill */
uart_b91_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)377 static int uart_b91_fifo_fill(const struct device *dev,
378 const uint8_t *tx_data,
379 int size)
380 {
381 int i = 0;
382 volatile struct uart_b91_t *uart = GET_UART(dev);
383
384 if (size > UART_DATA_SIZE) {
385 size = UART_DATA_SIZE;
386 }
387
388 for (i = 0; i < size; i++) {
389 if (uart_b91_get_rx_bufcnt(uart) != 0) {
390 break;
391 }
392
393 uart_b91_poll_out(dev, tx_data[i]);
394 }
395
396 return i;
397 }
398
399 /* API implementation: fifo_read */
uart_b91_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)400 static int uart_b91_fifo_read(const struct device *dev,
401 uint8_t *rx_data,
402 const int size)
403 {
404 int rx_count;
405 volatile struct uart_b91_t *uart = GET_UART(dev);
406
407 for (rx_count = 0; rx_count < size; rx_count++) {
408 if (uart_b91_get_rx_bufcnt(uart) == 0) {
409 break;
410 }
411
412 uart_b91_poll_in(dev, &rx_data[rx_count]);
413 }
414
415 return rx_count;
416 }
417
418 /* API implementation: irq_tx_enable */
uart_b91_irq_tx_enable(const struct device * dev)419 static void uart_b91_irq_tx_enable(const struct device *dev)
420 {
421 volatile struct uart_b91_t *uart = GET_UART(dev);
422
423 uart->ctrl3 = (uart->ctrl3 & (~FLD_UART_TX_IRQ_TRIQ_LEV)) |
424 BIT(FLD_UART_TX_IRQ_TRIQ_LEV_OFFSET);
425 uart->ctrl0 |= UART_TX_IRQ_MASK;
426 }
427
428 /* API implementation: irq_tx_disable */
uart_b91_irq_tx_disable(const struct device * dev)429 static void uart_b91_irq_tx_disable(const struct device *dev)
430 {
431 volatile struct uart_b91_t *uart = GET_UART(dev);
432
433 uart->ctrl0 &= ~UART_TX_IRQ_MASK;
434 }
435
436 /* API implementation: irq_tx_ready */
uart_b91_irq_tx_ready(const struct device * dev)437 static int uart_b91_irq_tx_ready(const struct device *dev)
438 {
439 volatile struct uart_b91_t *uart = GET_UART(dev);
440
441 return ((uart_b91_get_tx_bufcnt(uart) < UART_TX_BUF_CNT) &&
442 ((uart->ctrl0 & UART_TX_IRQ_MASK) != 0)) ? 1 : 0;
443 }
444
445 /* API implementation: irq_tx_complete */
uart_b91_irq_tx_complete(const struct device * dev)446 static int uart_b91_irq_tx_complete(const struct device *dev)
447 {
448 volatile struct uart_b91_t *uart = GET_UART(dev);
449
450 return (uart_b91_get_tx_bufcnt(uart) == 0) ? 1 : 0;
451 }
452
453 /* API implementation: irq_rx_enable */
uart_b91_irq_rx_enable(const struct device * dev)454 static void uart_b91_irq_rx_enable(const struct device *dev)
455 {
456 volatile struct uart_b91_t *uart = GET_UART(dev);
457
458 uart->ctrl3 = (uart->ctrl3 & (~FLD_UART_RX_IRQ_TRIQ_LEV)) |
459 BIT(FLD_UART_RX_IRQ_TRIQ_LEV_OFFSET);
460 uart->ctrl0 |= UART_RX_IRQ_MASK;
461 }
462
463 /* API implementation: irq_rx_disable */
uart_b91_irq_rx_disable(const struct device * dev)464 static void uart_b91_irq_rx_disable(const struct device *dev)
465 {
466 volatile struct uart_b91_t *uart = GET_UART(dev);
467
468 uart->ctrl0 &= ~UART_RX_IRQ_MASK;
469 }
470
471 /* API implementation: irq_rx_ready */
uart_b91_irq_rx_ready(const struct device * dev)472 static int uart_b91_irq_rx_ready(const struct device *dev)
473 {
474 volatile struct uart_b91_t *uart = GET_UART(dev);
475
476 return (uart_b91_get_rx_bufcnt(uart) > 0) ? 1 : 0;
477 }
478
479 /* API implementation: irq_err_enable */
uart_b91_irq_err_enable(const struct device * dev)480 static void uart_b91_irq_err_enable(const struct device *dev)
481 {
482 volatile struct uart_b91_t *uart = GET_UART(dev);
483
484 uart->rxtimeout |= UART_ERR_IRQ_MASK;
485 }
486
487 /* API implementation: irq_err_disable*/
uart_b91_irq_err_disable(const struct device * dev)488 static void uart_b91_irq_err_disable(const struct device *dev)
489 {
490 volatile struct uart_b91_t *uart = GET_UART(dev);
491
492 uart->rxtimeout &= ~UART_ERR_IRQ_MASK;
493 }
494
495 /* API implementation: irq_is_pending */
uart_b91_irq_is_pending(const struct device * dev)496 static int uart_b91_irq_is_pending(const struct device *dev)
497 {
498 volatile struct uart_b91_t *uart = GET_UART(dev);
499
500 return ((uart->status & UART_IRQ_STATUS) != 0) ? 1 : 0;
501 }
502
503 /* API implementation: irq_update */
uart_b91_irq_update(const struct device * dev)504 static int uart_b91_irq_update(const struct device *dev)
505 {
506 ARG_UNUSED(dev);
507
508 /* nothing to be done */
509 return 1;
510 }
511
512 /* API implementation: irq_callback_set */
uart_b91_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)513 static void uart_b91_irq_callback_set(const struct device *dev,
514 uart_irq_callback_user_data_t cb,
515 void *cb_data)
516 {
517 struct uart_b91_data *data = dev->data;
518
519 data->callback = cb;
520 data->cb_data = cb_data;
521 }
522
523 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
524
525 static const struct uart_driver_api uart_b91_driver_api = {
526 .poll_in = uart_b91_poll_in,
527 .poll_out = uart_b91_poll_out,
528 .err_check = uart_b91_err_check,
529 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
530 .configure = uart_b91_configure,
531 .config_get = uart_b91_config_get,
532 #endif
533 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
534 .fifo_fill = uart_b91_fifo_fill,
535 .fifo_read = uart_b91_fifo_read,
536 .irq_tx_enable = uart_b91_irq_tx_enable,
537 .irq_tx_disable = uart_b91_irq_tx_disable,
538 .irq_tx_ready = uart_b91_irq_tx_ready,
539 .irq_tx_complete = uart_b91_irq_tx_complete,
540 .irq_rx_enable = uart_b91_irq_rx_enable,
541 .irq_rx_disable = uart_b91_irq_rx_disable,
542 .irq_rx_ready = uart_b91_irq_rx_ready,
543 .irq_err_enable = uart_b91_irq_err_enable,
544 .irq_err_disable = uart_b91_irq_err_disable,
545 .irq_is_pending = uart_b91_irq_is_pending,
546 .irq_update = uart_b91_irq_update,
547 .irq_callback_set = uart_b91_irq_callback_set,
548 #endif
549 };
550
551
552 #define UART_B91_INIT(n) \
553 \
554 static void uart_b91_irq_connect_##n(void); \
555 \
556 PINCTRL_DT_INST_DEFINE(n); \
557 \
558 static const struct uart_b91_config uart_b91_cfg_##n = \
559 { \
560 .uart_addr = DT_INST_REG_ADDR(n), \
561 .baud_rate = DT_INST_PROP(n, current_speed), \
562 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
563 .pirq_connect = uart_b91_irq_connect_##n \
564 }; \
565 \
566 static struct uart_b91_data uart_b91_data_##n; \
567 \
568 DEVICE_DT_INST_DEFINE(n, uart_b91_driver_init, \
569 NULL, \
570 &uart_b91_data_##n, \
571 &uart_b91_cfg_##n, \
572 PRE_KERNEL_1, \
573 CONFIG_SERIAL_INIT_PRIORITY, \
574 (void *)&uart_b91_driver_api); \
575 \
576 static void uart_b91_irq_connect_##n(void) \
577 { \
578 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
579 uart_b91_irq_handler, \
580 DEVICE_DT_INST_GET(n), 0); \
581 \
582 riscv_plic_irq_enable(DT_INST_IRQN(n)); \
583 riscv_plic_set_priority(DT_INST_IRQN(n), DT_INST_IRQ(n, priority)); \
584 }
585
586 DT_INST_FOREACH_STATUS_OKAY(UART_B91_INIT)
587
