1 /*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_numaker_i2c
8
9 #include <zephyr/drivers/i2c.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/clock_control/clock_control_numaker.h>
12 #include <zephyr/drivers/reset.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/logging/log.h>
15
16 LOG_MODULE_REGISTER(i2c_numaker, CONFIG_I2C_LOG_LEVEL);
17
18 #include "i2c-priv.h"
19 #include <soc.h>
20 #include <NuMicro.h>
21
22 /* i2c Master Mode Status */
23 #define M_START 0x08 /* Start */
24 #define M_REPEAT_START 0x10 /* Master Repeat Start */
25 #define M_TRAN_ADDR_ACK 0x18 /* Master Transmit Address ACK */
26 #define M_TRAN_ADDR_NACK 0x20 /* Master Transmit Address NACK */
27 #define M_TRAN_DATA_ACK 0x28 /* Master Transmit Data ACK */
28 #define M_TRAN_DATA_NACK 0x30 /* Master Transmit Data NACK */
29 #define M_ARB_LOST 0x38 /* Master Arbitration Los */
30 #define M_RECE_ADDR_ACK 0x40 /* Master Receive Address ACK */
31 #define M_RECE_ADDR_NACK 0x48 /* Master Receive Address NACK */
32 #define M_RECE_DATA_ACK 0x50 /* Master Receive Data ACK */
33 #define M_RECE_DATA_NACK 0x58 /* Master Receive Data NACK */
34 #define BUS_ERROR 0x00 /* Bus error */
35
36 /* i2c Slave Mode Status */
37 #define S_REPEAT_START_STOP 0xA0 /* Slave Transmit Repeat Start or Stop */
38 #define S_TRAN_ADDR_ACK 0xA8 /* Slave Transmit Address ACK */
39 #define S_TRAN_DATA_ACK 0xB8 /* Slave Transmit Data ACK */
40 #define S_TRAN_DATA_NACK 0xC0 /* Slave Transmit Data NACK */
41 #define S_TRAN_LAST_DATA_ACK 0xC8 /* Slave Transmit Last Data ACK */
42 #define S_RECE_ADDR_ACK 0x60 /* Slave Receive Address ACK */
43 #define S_RECE_ARB_LOST 0x68 /* Slave Receive Arbitration Lost */
44 #define S_RECE_DATA_ACK 0x80 /* Slave Receive Data ACK */
45 #define S_RECE_DATA_NACK 0x88 /* Slave Receive Data NACK */
46
47 /* i2c GC Mode Status */
48 #define GC_ADDR_ACK 0x70 /* GC mode Address ACK */
49 #define GC_ARB_LOST 0x78 /* GC mode Arbitration Lost */
50 #define GC_DATA_ACK 0x90 /* GC mode Data ACK */
51 #define GC_DATA_NACK 0x98 /* GC mode Data NACK */
52
53 /* i2c Other Status */
54 #define ADDR_TRAN_ARB_LOST 0xB0 /* Address Transmit Arbitration Lost */
55 #define BUS_RELEASED 0xF8 /* Bus Released */
56
57 struct i2c_numaker_config {
58 I2C_T *i2c_base;
59 const struct reset_dt_spec reset;
60 uint32_t clk_modidx;
61 uint32_t clk_src;
62 uint32_t clk_div;
63 const struct device *clkctrl_dev;
64 uint32_t irq_n;
65 void (*irq_config_func)(const struct device *dev);
66 const struct pinctrl_dev_config *pincfg;
67 uint32_t bitrate;
68 };
69
70 struct i2c_numaker_data {
71 struct k_sem lock;
72 uint32_t dev_config;
73 /* Master transfer context */
74 struct {
75 struct k_sem xfer_sync;
76 uint16_t addr;
77 struct i2c_msg *msgs_beg;
78 struct i2c_msg *msgs_pos;
79 struct i2c_msg *msgs_end;
80 uint8_t *buf_beg;
81 uint8_t *buf_pos;
82 uint8_t *buf_end;
83 } master_xfer;
84 #ifdef CONFIG_I2C_TARGET
85 /* Slave transfer context */
86 struct {
87 struct i2c_target_config *slave_config;
88 bool slave_addressed;
89 } slave_xfer;
90 #endif
91 };
92
93 /* ACK/NACK last data byte, dependent on whether or not message merge is allowed */
m_numaker_i2c_master_xfer_msg_read_last_byte(const struct device * dev)94 static void m_numaker_i2c_master_xfer_msg_read_last_byte(const struct device *dev)
95 {
96 const struct i2c_numaker_config *config = dev->config;
97 struct i2c_numaker_data *data = dev->data;
98 I2C_T *i2c_base = config->i2c_base;
99
100 /* Shouldn't invoke with message pointer OOB */
101 __ASSERT_NO_MSG(data->master_xfer.msgs_pos < data->master_xfer.msgs_end);
102 /* Should invoke with exactly one data byte remaining for read */
103 __ASSERT_NO_MSG((data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ);
104 __ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 1);
105
106 /* Flags of previous message */
107 bool do_stop_prev = data->master_xfer.msgs_pos->flags & I2C_MSG_STOP;
108
109 /* Advance to next messages temporarily */
110 data->master_xfer.msgs_pos++;
111
112 /* Has next message? */
113 if (data->master_xfer.msgs_pos < data->master_xfer.msgs_end) {
114 /* Flags of next message */
115 struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
116 bool is_read_next = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
117 bool do_restart_next = data->master_xfer.msgs_pos->flags & I2C_MSG_RESTART;
118
119 /*
120 * Different R/W bit so message merge is disallowed.
121 * Force I2C Repeat Start on I2C Stop/Repeat Start missing
122 */
123 if (!is_read_next) {
124 if (!do_stop_prev && !do_restart_next) {
125 do_restart_next = true;
126 }
127 }
128
129 if (do_stop_prev || do_restart_next) {
130 /* NACK last data byte (required for Master Receiver) */
131 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
132 } else {
133 /* ACK last data byte, so to merge adjacent messages into one transaction */
134 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
135 }
136 } else {
137 /* NACK last data byte (required for Master Receiver) */
138 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
139 }
140
141 /* Roll back message pointer */
142 data->master_xfer.msgs_pos--;
143 }
144
145 /* End the transfer, involving I2C Stop and signal to thread */
m_numaker_i2c_master_xfer_end(const struct device * dev,bool do_stop)146 static void m_numaker_i2c_master_xfer_end(const struct device *dev, bool do_stop)
147 {
148 const struct i2c_numaker_config *config = dev->config;
149 struct i2c_numaker_data *data = dev->data;
150 I2C_T *i2c_base = config->i2c_base;
151
152 if (do_stop) {
153 /* Do I2C Stop */
154 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
155 }
156
157 /* Signal master transfer end */
158 k_sem_give(&data->master_xfer.xfer_sync);
159 }
160
161 static void m_numaker_i2c_master_xfer_msg_end(const struct device *dev);
162 /* Read next data byte, involving ACK/NACK last data byte and message merge */
m_numaker_i2c_master_xfer_msg_read_next_byte(const struct device * dev)163 static void m_numaker_i2c_master_xfer_msg_read_next_byte(const struct device *dev)
164 {
165 const struct i2c_numaker_config *config = dev->config;
166 struct i2c_numaker_data *data = dev->data;
167 I2C_T *i2c_base = config->i2c_base;
168
169 switch (data->master_xfer.buf_end - data->master_xfer.buf_pos) {
170 case 0:
171 /* Last data byte ACKed, we'll do message merge */
172 m_numaker_i2c_master_xfer_msg_end(dev);
173 break;
174 case 1:
175 /* Read last data byte for this message */
176 m_numaker_i2c_master_xfer_msg_read_last_byte(dev);
177 break;
178 default:
179 /* ACK non-last data byte */
180 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
181 }
182 }
183
184 /* End one message transfer, involving message merge and transfer end */
m_numaker_i2c_master_xfer_msg_end(const struct device * dev)185 static void m_numaker_i2c_master_xfer_msg_end(const struct device *dev)
186 {
187 const struct i2c_numaker_config *config = dev->config;
188 struct i2c_numaker_data *data = dev->data;
189 I2C_T *i2c_base = config->i2c_base;
190
191 /* Shouldn't invoke with message pointer OOB */
192 __ASSERT_NO_MSG(data->master_xfer.msgs_pos < data->master_xfer.msgs_end);
193 /* Should have transferred up */
194 __ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 0);
195
196 /* Flags of previous message */
197 bool is_read_prev = (data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
198 bool do_stop_prev = data->master_xfer.msgs_pos->flags & I2C_MSG_STOP;
199
200 /* Advance to next messages */
201 data->master_xfer.msgs_pos++;
202
203 /* Has next message? */
204 if (data->master_xfer.msgs_pos < data->master_xfer.msgs_end) {
205 /* Flags of next message */
206 struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
207 bool is_read_next = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
208 bool do_restart_next = data->master_xfer.msgs_pos->flags & I2C_MSG_RESTART;
209
210 /*
211 * Different R/W bit so message merge is disallowed.
212 * Force I2C Repeat Start on I2C Stop/Repeat Start missing
213 */
214 if (!is_read_prev != !is_read_next) { /* Logical XOR idiom */
215 if (!do_stop_prev && !do_restart_next) {
216 LOG_WRN("Cannot merge adjacent messages, force I2C Repeat Start");
217 do_restart_next = true;
218 }
219 }
220
221 if (do_stop_prev) {
222 /* Do I2C Stop and then Start */
223 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk |
224 I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
225 } else if (do_restart_next) {
226 /* Do I2C Repeat Start */
227 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
228 } else {
229 /* Merge into the same transaction */
230
231 /* Prepare buffer for current message */
232 data->master_xfer.buf_beg = data->master_xfer.msgs_pos->buf;
233 data->master_xfer.buf_pos = data->master_xfer.msgs_pos->buf;
234 data->master_xfer.buf_end = data->master_xfer.msgs_pos->buf +
235 data->master_xfer.msgs_pos->len;
236
237 if (is_read_prev) {
238 m_numaker_i2c_master_xfer_msg_read_next_byte(dev);
239 } else {
240 /*
241 * Interrupt flag not cleared, expect to re-enter ISR with
242 * context unchanged, except buffer changed for message change.
243 */
244 }
245 }
246 } else {
247 if (!do_stop_prev) {
248 LOG_WRN("Last message not marked I2C Stop");
249 }
250
251 m_numaker_i2c_master_xfer_end(dev, do_stop_prev);
252 }
253 }
254
i2c_numaker_configure(const struct device * dev,uint32_t dev_config)255 static int i2c_numaker_configure(const struct device *dev, uint32_t dev_config)
256 {
257 const struct i2c_numaker_config *config = dev->config;
258 struct i2c_numaker_data *data = dev->data;
259 uint32_t bitrate;
260
261 /* Check address size */
262 if (dev_config & I2C_ADDR_10_BITS) {
263 LOG_ERR("10-bits address not supported");
264 return -ENOTSUP;
265 }
266
267 switch (I2C_SPEED_GET(dev_config)) {
268 case I2C_SPEED_STANDARD:
269 bitrate = KHZ(100);
270 break;
271 case I2C_SPEED_FAST:
272 bitrate = KHZ(400);
273 break;
274 case I2C_SPEED_FAST_PLUS:
275 bitrate = MHZ(1);
276 break;
277 default:
278 LOG_ERR("Speed code %d not supported", I2C_SPEED_GET(dev_config));
279 return -ENOTSUP;
280 }
281
282 I2C_T *i2c_base = config->i2c_base;
283 int err = 0;
284
285 k_sem_take(&data->lock, K_FOREVER);
286 irq_disable(config->irq_n);
287
288 #ifdef CONFIG_I2C_TARGET
289 if (data->slave_xfer.slave_addressed) {
290 LOG_ERR("Reconfigure with slave being busy");
291 err = -EBUSY;
292 goto done;
293 }
294 #endif
295
296 I2C_Open(i2c_base, bitrate);
297 /* INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. */
298 i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk);
299 data->dev_config = dev_config;
300
301 done:
302
303 irq_enable(config->irq_n);
304 k_sem_give(&data->lock);
305
306 return err;
307 }
308
i2c_numaker_get_config(const struct device * dev,uint32_t * dev_config)309 static int i2c_numaker_get_config(const struct device *dev, uint32_t *dev_config)
310 {
311 struct i2c_numaker_data *data = dev->data;
312
313 if (!dev_config) {
314 return -EINVAL;
315 }
316
317 k_sem_take(&data->lock, K_FOREVER);
318 *dev_config = data->dev_config;
319 k_sem_give(&data->lock);
320
321 return 0;
322 }
323
324 /*
325 * Master active transfer:
326 * 1. Do I2C Start to start the transfer (thread)
327 * 2. I2C FSM (ISR)
328 * 3. Force I2C Stop to end the transfer (thread)
329 * Slave passive transfer:
330 * 1. Prepare callback (thread)
331 * 2. Do data transfer via above callback (ISR)
332 */
i2c_numaker_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)333 static int i2c_numaker_transfer(const struct device *dev, struct i2c_msg *msgs,
334 uint8_t num_msgs, uint16_t addr)
335 {
336 const struct i2c_numaker_config *config = dev->config;
337 struct i2c_numaker_data *data = dev->data;
338 I2C_T *i2c_base = config->i2c_base;
339 int err = 0;
340
341 k_sem_take(&data->lock, K_FOREVER);
342 irq_disable(config->irq_n);
343
344 if (data->slave_xfer.slave_addressed) {
345 LOG_ERR("Master transfer with slave being busy");
346 err = -EBUSY;
347 goto cleanup;
348 }
349
350 if (num_msgs == 0) {
351 goto cleanup;
352 }
353
354 /* Prepare to start transfer */
355 data->master_xfer.addr = addr;
356 data->master_xfer.msgs_beg = msgs;
357 data->master_xfer.msgs_pos = msgs;
358 data->master_xfer.msgs_end = msgs + num_msgs;
359
360 /* Do I2C Start to start the transfer */
361 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk);
362
363 irq_enable(config->irq_n);
364 k_sem_take(&data->master_xfer.xfer_sync, K_FOREVER);
365 irq_disable(config->irq_n);
366
367 /* Check transfer result */
368 if (data->master_xfer.msgs_pos != data->master_xfer.msgs_end) {
369 bool is_read;
370 bool is_10bit;
371
372 is_read = (data->master_xfer.msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
373 is_10bit = data->master_xfer.msgs_pos->flags & I2C_MSG_ADDR_10_BITS;
374 LOG_ERR("Failed message:");
375 LOG_ERR("MSG IDX: %d", data->master_xfer.msgs_pos - data->master_xfer.msgs_beg);
376 LOG_ERR("ADDR (%d-bit): 0x%04X", is_10bit ? 10 : 7, addr);
377 LOG_ERR("DIR: %s", is_read ? "R" : "W");
378 LOG_ERR("Expected %d bytes transferred, but actual %d",
379 data->master_xfer.msgs_pos->len,
380 data->master_xfer.buf_pos - data->master_xfer.buf_beg);
381 err = -EIO;
382 goto i2c_stop;
383 }
384
385 i2c_stop:
386
387 /* Do I2C Stop to release bus ownership */
388 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
389
390 #ifdef CONFIG_I2C_TARGET
391 /* Enable slave mode if one slave is registered */
392 if (data->slave_xfer.slave_config) {
393 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
394 }
395 #endif
396
397 cleanup:
398
399 irq_enable(config->irq_n);
400 k_sem_give(&data->lock);
401
402 return err;
403 }
404
405 #ifdef CONFIG_I2C_TARGET
i2c_numaker_slave_register(const struct device * dev,struct i2c_target_config * slave_config)406 static int i2c_numaker_slave_register(const struct device *dev,
407 struct i2c_target_config *slave_config)
408 {
409 if (!slave_config || !slave_config->callbacks) {
410 return -EINVAL;
411 }
412
413 if (slave_config->flags & I2C_ADDR_10_BITS) {
414 LOG_ERR("10-bits address not supported");
415 return -ENOTSUP;
416 }
417
418 const struct i2c_numaker_config *config = dev->config;
419 struct i2c_numaker_data *data = dev->data;
420 I2C_T *i2c_base = config->i2c_base;
421 int err = 0;
422
423 k_sem_take(&data->lock, K_FOREVER);
424 irq_disable(config->irq_n);
425
426 if (data->slave_xfer.slave_config) {
427 err = -EBUSY;
428 goto cleanup;
429 }
430
431 data->slave_xfer.slave_config = slave_config;
432 /* Slave address */
433 I2C_SetSlaveAddr(i2c_base,
434 0,
435 slave_config->address,
436 I2C_GCMODE_DISABLE);
437
438 /* Slave address state */
439 data->slave_xfer.slave_addressed = false;
440
441 /* Enable slave mode */
442 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
443
444 cleanup:
445
446 irq_enable(config->irq_n);
447 k_sem_give(&data->lock);
448
449 return err;
450 }
451
i2c_numaker_slave_unregister(const struct device * dev,struct i2c_target_config * slave_config)452 static int i2c_numaker_slave_unregister(const struct device *dev,
453 struct i2c_target_config *slave_config)
454 {
455 const struct i2c_numaker_config *config = dev->config;
456 struct i2c_numaker_data *data = dev->data;
457 I2C_T *i2c_base = config->i2c_base;
458 int err = 0;
459
460 if (!slave_config) {
461 return -EINVAL;
462 }
463
464 k_sem_take(&data->lock, K_FOREVER);
465 irq_disable(config->irq_n);
466
467 if (data->slave_xfer.slave_config != slave_config) {
468 err = -EINVAL;
469 goto cleanup;
470 }
471
472 if (data->slave_xfer.slave_addressed) {
473 LOG_ERR("Unregister slave driver with slave being busy");
474 err = -EBUSY;
475 goto cleanup;
476 }
477
478 /* Slave address: Zero */
479 I2C_SetSlaveAddr(i2c_base,
480 0,
481 0,
482 I2C_GCMODE_DISABLE);
483
484 /* Slave address state */
485 data->slave_xfer.slave_addressed = false;
486
487 /* Disable slave mode */
488 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
489 data->slave_xfer.slave_config = NULL;
490
491 cleanup:
492
493 irq_enable(config->irq_n);
494 k_sem_give(&data->lock);
495
496 return err;
497 }
498 #endif
499
i2c_numaker_recover_bus(const struct device * dev)500 static int i2c_numaker_recover_bus(const struct device *dev)
501 {
502 const struct i2c_numaker_config *config = dev->config;
503 struct i2c_numaker_data *data = dev->data;
504 I2C_T *i2c_base = config->i2c_base;
505
506 k_sem_take(&data->lock, K_FOREVER);
507 /* Do I2C Stop to release bus ownership */
508 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk);
509 k_sem_give(&data->lock);
510
511 return 0;
512 }
513
i2c_numaker_isr(const struct device * dev)514 static void i2c_numaker_isr(const struct device *dev)
515 {
516 const struct i2c_numaker_config *config = dev->config;
517 struct i2c_numaker_data *data = dev->data;
518 I2C_T *i2c_base = config->i2c_base;
519 #ifdef CONFIG_I2C_TARGET
520 struct i2c_target_config *slave_config = data->slave_xfer.slave_config;
521 const struct i2c_target_callbacks *slave_callbacks =
522 slave_config ? slave_config->callbacks : NULL;
523 uint8_t data_byte;
524 #endif
525 uint32_t status;
526
527 if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
528 I2C_ClearTimeoutFlag(i2c_base);
529 return;
530 }
531
532 status = I2C_GET_STATUS(i2c_base);
533
534 switch (status) {
535 case M_START: /* Start */
536 case M_REPEAT_START: /* Master Repeat Start */
537 /* Prepare buffer for current message */
538 data->master_xfer.buf_beg = data->master_xfer.msgs_pos->buf;
539 data->master_xfer.buf_pos = data->master_xfer.msgs_pos->buf;
540 data->master_xfer.buf_end = data->master_xfer.msgs_pos->buf +
541 data->master_xfer.msgs_pos->len;
542
543 /* Write I2C address */
544 struct i2c_msg *msgs_pos = data->master_xfer.msgs_pos;
545 bool is_read = (msgs_pos->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
546 uint16_t addr = data->master_xfer.addr;
547 int addr_rw = is_read ? ((addr << 1) | 1) : (addr << 1);
548
549 I2C_SET_DATA(i2c_base, (uint8_t) (addr_rw & 0xFF));
550 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
551 break;
552 case M_TRAN_ADDR_ACK: /* Master Transmit Address ACK */
553 case M_TRAN_DATA_ACK: /* Master Transmit Data ACK */
554 __ASSERT_NO_MSG(data->master_xfer.buf_pos);
555 if (data->master_xfer.buf_pos < data->master_xfer.buf_end) {
556 I2C_SET_DATA(i2c_base, *data->master_xfer.buf_pos++);
557 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
558 } else {
559 /* End this message */
560 m_numaker_i2c_master_xfer_msg_end(dev);
561 }
562 break;
563 case M_TRAN_ADDR_NACK: /* Master Transmit Address NACK */
564 case M_TRAN_DATA_NACK: /* Master Transmit Data NACK */
565 case M_RECE_ADDR_NACK: /* Master Receive Address NACK */
566 case M_ARB_LOST: /* Master Arbitration Lost */
567 m_numaker_i2c_master_xfer_end(dev, true);
568 break;
569 case M_RECE_ADDR_ACK: /* Master Receive Address ACK */
570 case M_RECE_DATA_ACK: /* Master Receive Data ACK */
571 __ASSERT_NO_MSG(data->master_xfer.buf_pos);
572
573 if (status == M_RECE_ADDR_ACK) {
574 __ASSERT_NO_MSG(data->master_xfer.buf_pos < data->master_xfer.buf_end);
575 } else if (status == M_RECE_DATA_ACK) {
576 __ASSERT_NO_MSG((data->master_xfer.buf_end -
577 data->master_xfer.buf_pos) >= 1);
578 *data->master_xfer.buf_pos++ = I2C_GET_DATA(i2c_base);
579 }
580
581 m_numaker_i2c_master_xfer_msg_read_next_byte(dev);
582 break;
583 case M_RECE_DATA_NACK: /* Master Receive Data NACK */
584 __ASSERT_NO_MSG((data->master_xfer.buf_end - data->master_xfer.buf_pos) == 1);
585 *data->master_xfer.buf_pos++ = I2C_GET_DATA(i2c_base);
586 /* End this message */
587 m_numaker_i2c_master_xfer_msg_end(dev);
588 break;
589 case BUS_ERROR: /* Bus error */
590 m_numaker_i2c_master_xfer_end(dev, true);
591 break;
592 #ifdef CONFIG_I2C_TARGET
593 /* NOTE: Don't disable interrupt here because slave mode relies on */
594 /* for passive transfer in ISR. */
595
596 /* Slave Transmit */
597 case S_TRAN_ADDR_ACK: /* Slave Transmit Address ACK */
598 case ADDR_TRAN_ARB_LOST: /* Slave Transmit Arbitration Lost */
599 data->slave_xfer.slave_addressed = true;
600 if (slave_callbacks->read_requested(slave_config, &data_byte) == 0) {
601 /* Non-last data byte */
602 I2C_SET_DATA(i2c_base, data_byte);
603 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
604 } else {
605 /* Go S_TRAN_LAST_DATA_ACK on error */
606 I2C_SET_DATA(i2c_base, 0xFF);
607 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
608 }
609 break;
610 case S_TRAN_DATA_ACK: /* Slave Transmit Data ACK */
611 if (slave_callbacks->read_processed(slave_config, &data_byte) == 0) {
612 /* Non-last data byte */
613 I2C_SET_DATA(i2c_base, data_byte);
614 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
615 } else {
616 /* Go S_TRAN_LAST_DATA_ACK on error */
617 I2C_SET_DATA(i2c_base, 0xFF);
618 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
619 }
620 break;
621 case S_TRAN_DATA_NACK: /* Slave Transmit Data NACK */
622 case S_TRAN_LAST_DATA_ACK: /* Slave Transmit Last Data ACK */
623 /* Go slave end */
624 data->slave_xfer.slave_addressed = false;
625 slave_callbacks->stop(slave_config);
626 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
627 break;
628 /* Slave Receive */
629 case S_RECE_DATA_ACK: /* Slave Receive Data ACK */
630 data_byte = I2C_GET_DATA(i2c_base);
631 if (slave_callbacks->write_received(slave_config, data_byte) == 0) {
632 /* Write OK, ACK next data byte */
633 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
634 } else {
635 /* Write FAILED, NACK next data byte */
636 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
637 }
638 break;
639 case S_RECE_DATA_NACK: /* Slave Receive Data NACK */
640 /* Go slave end */
641 data->slave_xfer.slave_addressed = false;
642 slave_callbacks->stop(slave_config);
643 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
644 break;
645 case S_RECE_ADDR_ACK: /* Slave Receive Address ACK */
646 case S_RECE_ARB_LOST: /* Slave Receive Arbitration Lost */
647 data->slave_xfer.slave_addressed = true;
648 if (slave_callbacks->write_requested(slave_config) == 0) {
649 /* Write ready, ACK next byte */
650 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
651 } else {
652 /* Write not ready, NACK next byte */
653 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk);
654 }
655 break;
656 case S_REPEAT_START_STOP: /* Slave Transmit/Receive Repeat Start or Stop */
657 /* Go slave end */
658 data->slave_xfer.slave_addressed = false;
659 slave_callbacks->stop(slave_config);
660 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk);
661 break;
662 #endif /* CONFIG_I2C_TARGET */
663
664 case BUS_RELEASED: /* Bus Released */
665 /* Ignore the interrupt raised by BUS_RELEASED. */
666 break;
667 default:
668 __ASSERT(false, "Uncaught I2C FSM state");
669 m_numaker_i2c_master_xfer_end(dev, true);
670 }
671 }
672
i2c_numaker_init(const struct device * dev)673 static int i2c_numaker_init(const struct device *dev)
674 {
675 const struct i2c_numaker_config *config = dev->config;
676 struct i2c_numaker_data *data = dev->data;
677 int err = 0;
678 struct numaker_scc_subsys scc_subsys;
679
680 /* Validate this module's reset object */
681 if (!device_is_ready(config->reset.dev)) {
682 LOG_ERR("reset controller not ready");
683 return -ENODEV;
684 }
685
686 /* Clean mutable context */
687 memset(data, 0x00, sizeof(*data));
688
689 k_sem_init(&data->lock, 1, 1);
690 k_sem_init(&data->master_xfer.xfer_sync, 0, 1);
691
692 SYS_UnlockReg();
693
694 memset(&scc_subsys, 0x00, sizeof(scc_subsys));
695 scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
696 scc_subsys.pcc.clk_modidx = config->clk_modidx;
697 scc_subsys.pcc.clk_src = config->clk_src;
698 scc_subsys.pcc.clk_div = config->clk_div;
699
700 /* Equivalent to CLK_EnableModuleClock() */
701 err = clock_control_on(config->clkctrl_dev, (clock_control_subsys_t) &scc_subsys);
702 if (err != 0) {
703 goto cleanup;
704 }
705 /* Equivalent to CLK_SetModuleClock() */
706 err = clock_control_configure(config->clkctrl_dev,
707 (clock_control_subsys_t) &scc_subsys,
708 NULL);
709 if (err != 0) {
710 goto cleanup;
711 }
712
713 /* Configure pinmux (NuMaker's SYS MFP) */
714 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
715 if (err != 0) {
716 goto cleanup;
717 }
718
719 /* Reset I2C to default state, same as BSP's SYS_ResetModule(id_rst) */
720 reset_line_toggle_dt(&config->reset);
721
722 err = i2c_numaker_configure(dev, I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
723 if (err != 0) {
724 goto cleanup;
725 }
726
727 config->irq_config_func(dev);
728
729 cleanup:
730
731 SYS_LockReg();
732 return err;
733 }
734
735 static const struct i2c_driver_api i2c_numaker_driver_api = {
736 .configure = i2c_numaker_configure,
737 .get_config = i2c_numaker_get_config,
738 .transfer = i2c_numaker_transfer,
739 #ifdef CONFIG_I2C_TARGET
740 .target_register = i2c_numaker_slave_register,
741 .target_unregister = i2c_numaker_slave_unregister,
742 #endif
743 .recover_bus = i2c_numaker_recover_bus,
744 };
745
746 #define I2C_NUMAKER_INIT(inst) \
747 PINCTRL_DT_INST_DEFINE(inst); \
748 \
749 static void i2c_numaker_irq_config_func_##inst(const struct device *dev) \
750 { \
751 IRQ_CONNECT(DT_INST_IRQN(inst), \
752 DT_INST_IRQ(inst, priority), \
753 i2c_numaker_isr, \
754 DEVICE_DT_INST_GET(inst), \
755 0); \
756 \
757 irq_enable(DT_INST_IRQN(inst)); \
758 } \
759 \
760 static const struct i2c_numaker_config i2c_numaker_config_##inst = { \
761 .i2c_base = (I2C_T *) DT_INST_REG_ADDR(inst), \
762 .reset = RESET_DT_SPEC_INST_GET(inst), \
763 .clk_modidx = DT_INST_CLOCKS_CELL(inst, clock_module_index), \
764 .clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
765 .clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
766 .clkctrl_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(inst))),\
767 .irq_n = DT_INST_IRQN(inst), \
768 .irq_config_func = i2c_numaker_irq_config_func_##inst, \
769 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
770 .bitrate = DT_INST_PROP(inst, clock_frequency), \
771 }; \
772 \
773 static struct i2c_numaker_data i2c_numaker_data_##inst; \
774 \
775 I2C_DEVICE_DT_INST_DEFINE(inst, \
776 i2c_numaker_init, \
777 NULL, \
778 &i2c_numaker_data_##inst, \
779 &i2c_numaker_config_##inst, \
780 POST_KERNEL, \
781 CONFIG_I2C_INIT_PRIORITY, \
782 &i2c_numaker_driver_api);
783
784 DT_INST_FOREACH_STATUS_OKAY(I2C_NUMAKER_INIT);
785
