Home
last modified time | relevance | path

Searched refs:HP_SRAM_WIN0_BASE (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/soc/intel/intel_adsp/ace/
Dmmu_ptl.c50 .start = (uint32_t)HP_SRAM_WIN0_BASE,
51 .end = (uint32_t)HP_SRAM_WIN0_BASE + (uint32_t)HP_SRAM_WIN0_SIZE,
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/common/include/
Dmem_window.h23 #define HP_SRAM_WIN0_BASE L2_SRAM_BASE + WIN0_OFFSET macro