1 /* 2 * Copyright (c) 2022 Intel Corp. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8 #ifndef _ADSP_MEMORY_WINDOW_H_ 9 #define _ADSP_MEMORY_WINDOW_H_ 10 11 #define WIN_SIZE(N) (CONFIG_MEMORY_WIN_##N##_SIZE) 12 13 #define MEM_WINDOW_NODE(n) DT_NODELABEL(mem_window##n) 14 #define WIN0_OFFSET DT_PROP(MEM_WINDOW_NODE(0), offset) 15 #define WIN1_OFFSET WIN0_OFFSET + WIN_SIZE(0) 16 #define WIN2_OFFSET WIN1_OFFSET + WIN_SIZE(1) 17 #define WIN3_OFFSET WIN2_OFFSET + WIN_SIZE(2) 18 19 20 21 #define WIN_OFFSET(n) (DT_PROP_OR(MEM_WINDOW_NODE(n), offset, (WIN##n##_OFFSET))) 22 23 #define HP_SRAM_WIN0_BASE L2_SRAM_BASE + WIN0_OFFSET 24 #define HP_SRAM_WIN0_SIZE WIN_SIZE(0) 25 26 #define HP_SRAM_WIN1_BASE L2_SRAM_BASE + WIN1_OFFSET 27 #define HP_SRAM_WIN1_SIZE WIN_SIZE(1) 28 29 #define HP_SRAM_WIN2_BASE L2_SRAM_BASE + WIN2_OFFSET 30 #define HP_SRAM_WIN2_SIZE WIN_SIZE(2) 31 32 #define HP_SRAM_WIN3_BASE L2_SRAM_BASE + WIN3_OFFSET 33 #define HP_SRAM_WIN3_SIZE WIN_SIZE(3) 34 35 #ifndef _LINKER 36 struct mem_win_config { 37 uint32_t base_addr; 38 uint32_t size; 39 uint32_t offset; 40 uint32_t mem_base; 41 bool initialize; 42 bool read_only; 43 }; 44 45 /** 46 * @brief Reinitializes device after power state change. 47 * Should be run on Primary Core only. 48 */ 49 void mem_window_idle_exit(void); 50 51 #endif 52 53 #endif 54
