1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/arch/xtensa/xtensa_mmu.h> 8 #include <zephyr/linker/linker-defs.h> 9 #include <adsp_memory.h> 10 #include <adsp_imr_layout.h> 11 12 #include <inttypes.h> 13 14 extern char _cached_start[]; 15 extern char _cached_end[]; 16 extern char _imr_start[]; 17 extern char _imr_end[]; 18 extern char __common_rom_region_start[]; 19 extern char __common_rom_region_end[]; 20 extern char __common_ram_region_start[]; 21 extern char __common_ram_region_end[]; 22 23 const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = { 24 { 25 .start = (uint32_t)__common_ram_region_start, 26 .end = (uint32_t)__common_ram_region_end, 27 .attrs = XTENSA_MMU_PERM_W, 28 .name = "common-ram", 29 }, 30 { 31 /* Workaround for D3 flows. L2 TLB wider than MMU TLB */ 32 .start = (uint32_t)L2_SRAM_BASE, 33 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM, 34 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 35 .name = "workaround L2 TLB/MMU TLB", 36 }, 37 { 38 .start = (uint32_t)VECBASE_RESET_PADDR_SRAM, 39 .end = (uint32_t)VECBASE_RESET_PADDR_SRAM + VECTOR_TBL_SIZE, 40 .attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_MAP_SHARED, 41 .name = "exceptions", 42 }, 43 { 44 .start = (uint32_t)_cached_start, 45 .end = (uint32_t)_cached_end, 46 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 47 .name = "cached", 48 }, 49 { 50 .start = (uint32_t)HP_SRAM_WIN0_BASE, 51 .end = (uint32_t)HP_SRAM_WIN0_BASE + (uint32_t)HP_SRAM_WIN0_SIZE, 52 .attrs = XTENSA_MMU_PERM_W, 53 .name = "win0", 54 }, 55 { 56 .start = (uint32_t)HP_SRAM_WIN1_BASE, 57 .end = (uint32_t)HP_SRAM_WIN1_BASE + (uint32_t)HP_SRAM_WIN1_SIZE, 58 .attrs = XTENSA_MMU_PERM_W, 59 .name = "win2", 60 }, 61 { 62 .start = (uint32_t)HP_SRAM_WIN2_BASE, 63 .end = (uint32_t)HP_SRAM_WIN2_BASE + (uint32_t)HP_SRAM_WIN2_SIZE, 64 .attrs = XTENSA_MMU_PERM_W, 65 .name = "win2", 66 }, 67 { 68 .start = (uint32_t)HP_SRAM_WIN3_BASE, 69 .end = (uint32_t)HP_SRAM_WIN3_BASE + (uint32_t)HP_SRAM_WIN3_SIZE, 70 .attrs = XTENSA_MMU_PERM_W, 71 .name = "win3", 72 }, 73 /* Map IMR */ 74 { 75 .start = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE - IMR_BOOT_LDR_MANIFEST_SIZE), 76 .end = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE, 77 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 78 .name = "imr stack", 79 }, 80 { 81 .start = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE, 82 .end = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE), 83 .name = "imr text", 84 }, 85 { 86 .start = (uint32_t)IMR_BOOT_LDR_BSS_BASE, 87 .end = (uint32_t)(IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE), 88 .name = "imr bss", 89 }, 90 { 91 .start = (uint32_t)IMR_BOOT_LDR_TEXT_ENTRY_BASE, 92 .end = (uint32_t)(IMR_BOOT_LDR_TEXT_ENTRY_BASE + IMR_BOOT_LDR_TEXT_ENTRY_SIZE), 93 .attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_MAP_SHARED, 94 .name = "imr text", 95 }, 96 { 97 .start = (uint32_t)IMR_BOOT_LDR_STACK_BASE, 98 .end = (uint32_t)(IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE), 99 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 100 .name = "imr stack", 101 }, 102 { 103 .start = (uint32_t)IMR_LAYOUT_ADDRESS, 104 /* sizeof(struct imr_layout) happens to be 0x1000 (4096) bytes. */ 105 .end = (uint32_t)(IMR_LAYOUT_ADDRESS + sizeof(struct imr_layout)), 106 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 107 .name = "imr layout", 108 }, 109 { 110 .start = (uint32_t)IMR_L3_HEAP_BASE, 111 .end = (uint32_t)(IMR_L3_HEAP_BASE + IMR_L3_HEAP_SIZE), 112 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 113 .name = "imr L3 heap", 114 }, 115 { 116 .start = (uint32_t)LP_SRAM_BASE, 117 .end = (uint32_t)(LP_SRAM_BASE + LP_SRAM_SIZE), 118 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 119 .name = "lpsram", 120 }, 121 { 122 .start = (uint32_t)(ADSP_L1CC_ADDR), 123 .end = (uint32_t)(ADSP_L1CC_ADDR + CONFIG_MMU_PAGE_SIZE), 124 .attrs = XTENSA_MMU_PERM_W, 125 .name = "l1cc", 126 }, 127 { 128 /* FIXME: definitely need more refinements... */ 129 .start = (uint32_t)0x0, 130 .end = (uint32_t)0x100000, 131 .attrs = XTENSA_MMU_PERM_W, 132 .name = "hwreg0", 133 }, 134 { 135 /* FIXME: definitely need more refinements... */ 136 .start = (uint32_t)0x170000, 137 .end = (uint32_t)0x180000, 138 .attrs = XTENSA_MMU_PERM_W, 139 .name = "hwreg1", 140 }, 141 }; 142 143 int xtensa_soc_mmu_ranges_num = ARRAY_SIZE(xtensa_soc_mmu_ranges); 144
