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Searched refs:CPG_CORE (Results 1 – 9 of 9) sorted by relevance

/Zephyr-Core-3.7.0/dts/arm/renesas/rcar/gen3/
Dr8a77951.dtsi20 <&cpg CPG_CORE R8A7795_CLK_CANFD>;
25 <&cpg CPG_CORE R8A7795_CLK_S0D12>;
30 <&cpg CPG_CORE R8A7795_CLK_S3D4>;
35 <&cpg CPG_CORE R8A7795_CLK_S3D4>;
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/clock/
Drenesas_cpg_mssr.h10 #define CPG_CORE 0 /* Core Clock */ macro
/Zephyr-Core-3.7.0/dts/arm64/renesas/
Drcar_gen3_ca57.dtsi92 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
104 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
119 <&cpg CPG_CORE R8A7795_CLK_S3D4>;
Dr8a779f0.dtsi97 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
114 clocks = <&cpg CPG_MOD 514>, <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>;
/Zephyr-Core-3.7.0/dts/arm/renesas/rcar/gen4/
Dr8a779f0.dtsi61 clocks = <&cpg CPG_MOD 702>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
67 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c158 } else if (clk->domain == CPG_CORE) { in r8a779f0_cpg_mssr_start_stop()
270 .cmn.clk_info_table[CPG_CORE] = core_props, \
271 .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
Dclock_control_r8a7795_cpg_mssr.c164 } else if (clk->domain == CPG_CORE) { in r8a7795_cpg_mssr_start_stop()
279 .cmn.clk_info_table[CPG_CORE] = core_props, \
280 .cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props), \
Dclock_control_renesas_cpg_mssr.h52 .domain = CPG_CORE, \
Dclock_control_renesas_cpg_mssr.c374 parent = rcar_cpg_find_clk_info_by_module_id(dev, CPG_CORE, in rcar_cpg_build_clock_relationship()