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Searched refs:sys_clk_freq (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/drivers/serial/
Duart_cmsdk_apb.c66 uint32_t sys_clk_freq; member
108 if ((dev_data->baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) { in baudrate_set()
110 dev_cfg->uart->bauddiv = (dev_cfg->sys_clk_freq / dev_data->baud_rate); in baudrate_set()
486 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
551 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
616 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
681 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(3, clocks, clock_frequency),
746 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(4, clocks, clock_frequency),
Duart_sifive.c54 uint32_t sys_clk_freq; member
337 uart->div = cfg->sys_clk_freq / cfg->baud_rate - 1; in uart_sifive_init()
391 .sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
434 .sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
Duart_stellaris.c73 uint32_t sys_clk_freq; member
229 config->sys_clk_freq); in uart_stellaris_init()
584 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
623 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
662 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
Duart_miv.c134 uint32_t sys_clk_freq; member
350 uint16_t baud_value = (cfg->sys_clk_freq / (cfg->baud_rate * 16U)) - 1; in uart_miv_init()
400 .sys_clk_freq = DT_INST_PROP(0, clock_frequency),
Duart_cc23x0.c22 uint32_t sys_clk_freq; member
142 UARTConfigSetExpClk(config->reg, config->sys_clk_freq, cfg->baudrate, line_ctrl); in uart_cc23x0_configure()
388 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
Duart_cdns.h132 uint32_t sys_clk_freq; member
Duart_cdns.c51 uart_regs->baud_rate_gen = (dev_cfg->sys_clk_freq + ((dev_cfg->bdiv + 1) * baud_rate) / 2) / in uart_cdns_set_baudrate()
298 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
Duart_cc32xx.c24 uint32_t sys_clk_freq; member
330 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency),\
Duart_cc13xx_cc26xx.c27 uint32_t sys_clk_freq; member
167 config->sys_clk_freq, cfg->baudrate, in uart_cc13xx_cc26xx_configure()
612 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, \
Duart_mchp_xec.c184 uint32_t sys_clk_freq; member
296 if ((baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) { in set_baud_rate()
301 divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3)) in set_baud_rate()
1088 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
Duart_xlnx_ps.c142 uint32_t sys_clk_freq; member
234 uint32_t clk_freq = dev_cfg->sys_clk_freq; in set_baudrate()
1208 .sys_clk_freq = DT_INST_PROP(port, clock_frequency), \
Duart_ns16550.c335 uint32_t sys_clk_freq; member
615 if (dev_cfg->sys_clk_freq != 0U) {
616 pclk = dev_cfg->sys_clk_freq;
1349 if (dev_cfg->sys_clk_freq != 0U) {
1350 pclk = dev_cfg->sys_clk_freq;
1936 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1940 .sys_clk_freq = 0, \