1 /*
2 * Copyright (c) 2019 Brett Witherspoon
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ti_cc13xx_cc26xx_uart
8
9 #include <zephyr/device.h>
10 #include <errno.h>
11 #include <zephyr/sys/__assert.h>
12 #include <zephyr/sys/atomic.h>
13 #include <zephyr/pm/device.h>
14 #include <zephyr/pm/policy.h>
15 #include <zephyr/drivers/uart.h>
16 #include <zephyr/drivers/pinctrl.h>
17
18 #include <driverlib/prcm.h>
19 #include <driverlib/uart.h>
20
21 #include <ti/drivers/Power.h>
22 #include <ti/drivers/power/PowerCC26X2.h>
23 #include <zephyr/irq.h>
24
25 struct uart_cc13xx_cc26xx_config {
26 uint32_t reg;
27 uint32_t sys_clk_freq;
28 };
29
30 enum uart_cc13xx_cc26xx_pm_locks {
31 UART_CC13XX_CC26XX_PM_LOCK_TX,
32 UART_CC13XX_CC26XX_PM_LOCK_RX,
33 UART_CC13XX_CC26XX_PM_LOCK_COUNT,
34 };
35
36 struct uart_cc13xx_cc26xx_data {
37 struct uart_config uart_config;
38 const struct pinctrl_dev_config *pcfg;
39 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
40 uart_irq_callback_user_data_t callback;
41 void *user_data;
42 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
43 #ifdef CONFIG_PM
44 Power_NotifyObj postNotify;
45 ATOMIC_DEFINE(pm_lock, UART_CC13XX_CC26XX_PM_LOCK_COUNT);
46 #endif
47 };
48
uart_cc13xx_cc26xx_poll_in(const struct device * dev,unsigned char * c)49 static int uart_cc13xx_cc26xx_poll_in(const struct device *dev,
50 unsigned char *c)
51 {
52 const struct uart_cc13xx_cc26xx_config *config = dev->config;
53
54 if (!UARTCharsAvail(config->reg)) {
55 return -1;
56 }
57
58 *c = UARTCharGetNonBlocking(config->reg);
59
60 return 0;
61 }
62
uart_cc13xx_cc26xx_poll_out(const struct device * dev,unsigned char c)63 static void uart_cc13xx_cc26xx_poll_out(const struct device *dev,
64 unsigned char c)
65 {
66 const struct uart_cc13xx_cc26xx_config *config = dev->config;
67
68 UARTCharPut(config->reg, c);
69 /*
70 * Need to wait for character to be transmitted to ensure cpu does not
71 * enter standby when uart is busy
72 */
73 while (UARTBusy(config->reg) == true) {
74 }
75 }
76
uart_cc13xx_cc26xx_err_check(const struct device * dev)77 static int uart_cc13xx_cc26xx_err_check(const struct device *dev)
78 {
79 const struct uart_cc13xx_cc26xx_config *config = dev->config;
80
81 uint32_t flags = UARTRxErrorGet(config->reg);
82
83 int error = (flags & UART_RXERROR_FRAMING ? UART_ERROR_FRAMING : 0) |
84 (flags & UART_RXERROR_PARITY ? UART_ERROR_PARITY : 0) |
85 (flags & UART_RXERROR_BREAK ? UART_BREAK : 0) |
86 (flags & UART_RXERROR_OVERRUN ? UART_ERROR_OVERRUN : 0);
87
88 UARTRxErrorClear(config->reg);
89
90 return error;
91 }
92
uart_cc13xx_cc26xx_configure(const struct device * dev,const struct uart_config * cfg)93 static int uart_cc13xx_cc26xx_configure(const struct device *dev,
94 const struct uart_config *cfg)
95 {
96 const struct uart_cc13xx_cc26xx_config *config = dev->config;
97 struct uart_cc13xx_cc26xx_data *data = dev->data;
98 uint32_t line_ctrl = 0;
99 bool flow_ctrl;
100
101 switch (cfg->parity) {
102 case UART_CFG_PARITY_NONE:
103 line_ctrl |= UART_CONFIG_PAR_NONE;
104 break;
105 case UART_CFG_PARITY_ODD:
106 line_ctrl |= UART_CONFIG_PAR_ODD;
107 break;
108 case UART_CFG_PARITY_EVEN:
109 line_ctrl |= UART_CONFIG_PAR_EVEN;
110 break;
111 case UART_CFG_PARITY_MARK:
112 line_ctrl |= UART_CONFIG_PAR_ONE;
113 break;
114 case UART_CFG_PARITY_SPACE:
115 line_ctrl |= UART_CONFIG_PAR_ZERO;
116 break;
117 default:
118 return -EINVAL;
119 }
120
121 switch (cfg->stop_bits) {
122 case UART_CFG_STOP_BITS_1:
123 line_ctrl |= UART_CONFIG_STOP_ONE;
124 break;
125 case UART_CFG_STOP_BITS_2:
126 line_ctrl |= UART_CONFIG_STOP_TWO;
127 break;
128 case UART_CFG_STOP_BITS_0_5:
129 case UART_CFG_STOP_BITS_1_5:
130 return -ENOTSUP;
131 default:
132 return -EINVAL;
133 }
134
135 switch (cfg->data_bits) {
136 case UART_CFG_DATA_BITS_5:
137 line_ctrl |= UART_CONFIG_WLEN_5;
138 break;
139 case UART_CFG_DATA_BITS_6:
140 line_ctrl |= UART_CONFIG_WLEN_6;
141 break;
142 case UART_CFG_DATA_BITS_7:
143 line_ctrl |= UART_CONFIG_WLEN_7;
144 break;
145 case UART_CFG_DATA_BITS_8:
146 line_ctrl |= UART_CONFIG_WLEN_8;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 switch (cfg->flow_ctrl) {
153 case UART_CFG_FLOW_CTRL_NONE:
154 flow_ctrl = false;
155 break;
156 case UART_CFG_FLOW_CTRL_RTS_CTS:
157 flow_ctrl = true;
158 break;
159 case UART_CFG_FLOW_CTRL_DTR_DSR:
160 return -ENOTSUP;
161 default:
162 return -EINVAL;
163 }
164
165 /* Disables UART before setting control registers */
166 UARTConfigSetExpClk(config->reg,
167 config->sys_clk_freq, cfg->baudrate,
168 line_ctrl);
169
170 /* Clear all UART interrupts */
171 UARTIntClear(config->reg,
172 UART_INT_OE | UART_INT_BE | UART_INT_PE |
173 UART_INT_FE | UART_INT_RT | UART_INT_TX |
174 UART_INT_RX | UART_INT_CTS);
175
176 if (flow_ctrl) {
177 UARTHwFlowControlEnable(config->reg);
178 } else {
179 UARTHwFlowControlDisable(config->reg);
180 }
181
182 /* Re-enable UART */
183 UARTEnable(config->reg);
184
185 /* Disabled FIFOs act as 1-byte-deep holding registers (character mode) */
186 UARTFIFODisable(config->reg);
187
188 data->uart_config = *cfg;
189
190 return 0;
191 }
192
193 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_cc13xx_cc26xx_config_get(const struct device * dev,struct uart_config * cfg)194 static int uart_cc13xx_cc26xx_config_get(const struct device *dev,
195 struct uart_config *cfg)
196 {
197 struct uart_cc13xx_cc26xx_data *data = dev->data;
198
199 *cfg = data->uart_config;
200 return 0;
201 }
202 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
203
204 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
205
uart_cc13xx_cc26xx_fifo_fill(const struct device * dev,const uint8_t * buf,int len)206 static int uart_cc13xx_cc26xx_fifo_fill(const struct device *dev,
207 const uint8_t *buf,
208 int len)
209 {
210 const struct uart_cc13xx_cc26xx_config *config = dev->config;
211 int n = 0;
212
213 while (n < len) {
214 if (!UARTCharPutNonBlocking(config->reg, buf[n])) {
215 break;
216 }
217 n++;
218 }
219
220 return n;
221 }
222
uart_cc13xx_cc26xx_fifo_read(const struct device * dev,uint8_t * buf,const int len)223 static int uart_cc13xx_cc26xx_fifo_read(const struct device *dev,
224 uint8_t *buf,
225 const int len)
226 {
227 const struct uart_cc13xx_cc26xx_config *config = dev->config;
228 int c, n;
229
230 n = 0;
231 while (n < len) {
232 c = UARTCharGetNonBlocking(config->reg);
233 if (c == -1) {
234 break;
235 }
236 buf[n++] = c;
237 }
238
239 return n;
240 }
241
uart_cc13xx_cc26xx_irq_tx_enable(const struct device * dev)242 static void uart_cc13xx_cc26xx_irq_tx_enable(const struct device *dev)
243 {
244 const struct uart_cc13xx_cc26xx_config *config = dev->config;
245
246 #ifdef CONFIG_PM
247 struct uart_cc13xx_cc26xx_data *data = dev->data;
248
249 if (!atomic_test_and_set_bit(data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_TX)) {
250 /*
251 * When tx irq is enabled, it is implicit that we are expecting
252 * to transmit using the uart, hence we should no longer go
253 * into standby.
254 *
255 * Instead of using pm_device_busy_set(), which currently does
256 * not impact the PM policy, we specifically disable the
257 * standby mode instead, since it is the power state that
258 * would interfere with a transfer.
259 */
260 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
261 }
262 #endif
263
264 UARTIntEnable(config->reg, UART_INT_TX);
265 }
266
uart_cc13xx_cc26xx_irq_tx_disable(const struct device * dev)267 static void uart_cc13xx_cc26xx_irq_tx_disable(const struct device *dev)
268 {
269 const struct uart_cc13xx_cc26xx_config *config = dev->config;
270
271 UARTIntDisable(config->reg, UART_INT_TX);
272
273 #ifdef CONFIG_PM
274 struct uart_cc13xx_cc26xx_data *data = dev->data;
275
276 if (atomic_test_and_clear_bit(data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_TX)) {
277 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
278 }
279 #endif
280 }
281
uart_cc13xx_cc26xx_irq_tx_ready(const struct device * dev)282 static int uart_cc13xx_cc26xx_irq_tx_ready(const struct device *dev)
283 {
284 const struct uart_cc13xx_cc26xx_config *config = dev->config;
285
286 return UARTSpaceAvail(config->reg) ? 1 : 0;
287 }
288
uart_cc13xx_cc26xx_irq_rx_enable(const struct device * dev)289 static void uart_cc13xx_cc26xx_irq_rx_enable(const struct device *dev)
290 {
291 const struct uart_cc13xx_cc26xx_config *config = dev->config;
292
293 #ifdef CONFIG_PM
294 struct uart_cc13xx_cc26xx_data *data = dev->data;
295
296 /*
297 * When rx is enabled, it is implicit that we are expecting
298 * to receive from the uart, hence we can no longer go into
299 * standby.
300 */
301 if (!atomic_test_and_set_bit(data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_RX)) {
302 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
303 }
304 #endif
305
306 UARTIntEnable(config->reg, UART_INT_RX);
307 }
308
uart_cc13xx_cc26xx_irq_rx_disable(const struct device * dev)309 static void uart_cc13xx_cc26xx_irq_rx_disable(const struct device *dev)
310 {
311 const struct uart_cc13xx_cc26xx_config *config = dev->config;
312
313 #ifdef CONFIG_PM
314 struct uart_cc13xx_cc26xx_data *data = dev->data;
315
316 if (atomic_test_and_clear_bit(data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_RX)) {
317 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
318 }
319 #endif
320
321 UARTIntDisable(config->reg, UART_INT_RX);
322 }
323
uart_cc13xx_cc26xx_irq_tx_complete(const struct device * dev)324 static int uart_cc13xx_cc26xx_irq_tx_complete(const struct device *dev)
325 {
326 const struct uart_cc13xx_cc26xx_config *config = dev->config;
327
328 return UARTBusy(config->reg) ? 0 : 1;
329 }
330
uart_cc13xx_cc26xx_irq_rx_ready(const struct device * dev)331 static int uart_cc13xx_cc26xx_irq_rx_ready(const struct device *dev)
332 {
333 const struct uart_cc13xx_cc26xx_config *config = dev->config;
334
335 return UARTCharsAvail(config->reg) ? 1 : 0;
336 }
337
uart_cc13xx_cc26xx_irq_err_enable(const struct device * dev)338 static void uart_cc13xx_cc26xx_irq_err_enable(const struct device *dev)
339 {
340 const struct uart_cc13xx_cc26xx_config *config = dev->config;
341
342 UARTIntEnable(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
343 }
344
uart_cc13xx_cc26xx_irq_err_disable(const struct device * dev)345 static void uart_cc13xx_cc26xx_irq_err_disable(const struct device *dev)
346 {
347 const struct uart_cc13xx_cc26xx_config *config = dev->config;
348
349 UARTIntDisable(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
350 }
351
uart_cc13xx_cc26xx_irq_is_pending(const struct device * dev)352 static int uart_cc13xx_cc26xx_irq_is_pending(const struct device *dev)
353 {
354 const struct uart_cc13xx_cc26xx_config *config = dev->config;
355 uint32_t status = UARTIntStatus(config->reg, true);
356
357 return status & (UART_INT_TX | UART_INT_RX) ? 1 : 0;
358 }
359
uart_cc13xx_cc26xx_irq_update(const struct device * dev)360 static int uart_cc13xx_cc26xx_irq_update(const struct device *dev)
361 {
362 ARG_UNUSED(dev);
363 return 1;
364 }
365
uart_cc13xx_cc26xx_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * user_data)366 static void uart_cc13xx_cc26xx_irq_callback_set(const struct device *dev,
367 uart_irq_callback_user_data_t cb,
368 void *user_data)
369 {
370 struct uart_cc13xx_cc26xx_data *data = dev->data;
371
372 data->callback = cb;
373 data->user_data = user_data;
374 }
375
uart_cc13xx_cc26xx_isr(const struct device * dev)376 static void uart_cc13xx_cc26xx_isr(const struct device *dev)
377 {
378 struct uart_cc13xx_cc26xx_data *data = dev->data;
379
380 if (data->callback) {
381 data->callback(dev, data->user_data);
382 }
383 }
384
385 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
386
387 #ifdef CONFIG_PM
388 /*
389 * ======== postNotifyFxn ========
390 * Called by Power module when waking up the CPU from Standby, to support
391 * the case when PM is set but PM_DEVICE is
392 * not. The uart needs to be reconfigured afterwards unless Zephyr's device
393 * PM turned it off, in which case it'd be responsible for turning it back
394 * on and reconfiguring it.
395 */
postNotifyFxn(unsigned int eventType,uintptr_t eventArg,uintptr_t clientArg)396 static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg,
397 uintptr_t clientArg)
398 {
399 const struct device *dev = (const struct device *)clientArg;
400 const struct uart_cc13xx_cc26xx_config *config = dev->config;
401 struct uart_cc13xx_cc26xx_data *data = dev->data;
402 int ret = Power_NOTIFYDONE;
403 int16_t res_id;
404
405 /* Reconfigure the hardware if returning from standby */
406 if (eventType == PowerCC26XX_AWAKE_STANDBY) {
407 if (config->reg == DT_INST_REG_ADDR(0)) {
408 res_id = PowerCC26XX_PERIPH_UART0;
409 } else { /* DT_INST_REG_ADDR(1) */
410 res_id = PowerCC26X2_PERIPH_UART1;
411 }
412
413 if (Power_getDependencyCount(res_id) != 0) {
414 /*
415 * Reconfigure and enable UART only if not
416 * actively powered down
417 */
418 if (uart_cc13xx_cc26xx_configure(dev,
419 &data->uart_config) != 0) {
420 ret = Power_NOTIFYERROR;
421 }
422 }
423 }
424
425 return (ret);
426 }
427 #endif
428
429 #ifdef CONFIG_PM_DEVICE
uart_cc13xx_cc26xx_pm_action(const struct device * dev,enum pm_device_action action)430 static int uart_cc13xx_cc26xx_pm_action(const struct device *dev,
431 enum pm_device_action action)
432 {
433 const struct uart_cc13xx_cc26xx_config *config = dev->config;
434 struct uart_cc13xx_cc26xx_data *data = dev->data;
435 int ret = 0;
436
437 switch (action) {
438 case PM_DEVICE_ACTION_RESUME:
439 if (config->reg == DT_INST_REG_ADDR(0)) {
440 Power_setDependency(PowerCC26XX_PERIPH_UART0);
441 } else {
442 Power_setDependency(PowerCC26X2_PERIPH_UART1);
443 }
444 /* Configure and enable UART */
445 ret = uart_cc13xx_cc26xx_configure(dev, &data->uart_config);
446 break;
447 case PM_DEVICE_ACTION_SUSPEND:
448 UARTDisable(config->reg);
449 /*
450 * Release power dependency - i.e. potentially power
451 * down serial domain.
452 */
453 if (config->reg == DT_INST_REG_ADDR(0)) {
454 Power_releaseDependency(PowerCC26XX_PERIPH_UART0);
455 } else {
456 Power_releaseDependency(PowerCC26X2_PERIPH_UART1);
457 }
458 break;
459 default:
460 return -ENOTSUP;
461 }
462
463 return ret;
464 }
465 #endif /* CONFIG_PM_DEVICE */
466
467 static DEVICE_API(uart, uart_cc13xx_cc26xx_driver_api) = {
468 .poll_in = uart_cc13xx_cc26xx_poll_in,
469 .poll_out = uart_cc13xx_cc26xx_poll_out,
470 .err_check = uart_cc13xx_cc26xx_err_check,
471 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
472 .configure = uart_cc13xx_cc26xx_configure,
473 .config_get = uart_cc13xx_cc26xx_config_get,
474 #endif
475 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
476 .fifo_fill = uart_cc13xx_cc26xx_fifo_fill,
477 .fifo_read = uart_cc13xx_cc26xx_fifo_read,
478 .irq_tx_enable = uart_cc13xx_cc26xx_irq_tx_enable,
479 .irq_tx_disable = uart_cc13xx_cc26xx_irq_tx_disable,
480 .irq_tx_ready = uart_cc13xx_cc26xx_irq_tx_ready,
481 .irq_rx_enable = uart_cc13xx_cc26xx_irq_rx_enable,
482 .irq_rx_disable = uart_cc13xx_cc26xx_irq_rx_disable,
483 .irq_tx_complete = uart_cc13xx_cc26xx_irq_tx_complete,
484 .irq_rx_ready = uart_cc13xx_cc26xx_irq_rx_ready,
485 .irq_err_enable = uart_cc13xx_cc26xx_irq_err_enable,
486 .irq_err_disable = uart_cc13xx_cc26xx_irq_err_disable,
487 .irq_is_pending = uart_cc13xx_cc26xx_irq_is_pending,
488 .irq_update = uart_cc13xx_cc26xx_irq_update,
489 .irq_callback_set = uart_cc13xx_cc26xx_irq_callback_set,
490 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
491 };
492
493 #ifdef CONFIG_PM
494 #define UART_CC13XX_CC26XX_POWER_UART(n) \
495 do { \
496 struct uart_cc13xx_cc26xx_data *dev_data = dev->data; \
497 \
498 atomic_clear_bit(dev_data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_RX); \
499 atomic_clear_bit(dev_data->pm_lock, UART_CC13XX_CC26XX_PM_LOCK_TX); \
500 \
501 /* Set Power dependencies */ \
502 if (DT_INST_REG_ADDR(n) == 0x40001000) { \
503 Power_setDependency(PowerCC26XX_PERIPH_UART0); \
504 } else { \
505 Power_setDependency(PowerCC26X2_PERIPH_UART1); \
506 } \
507 \
508 /* Register notification function */ \
509 Power_registerNotify(&dev_data->postNotify, \
510 PowerCC26XX_AWAKE_STANDBY, \
511 postNotifyFxn, (uintptr_t)dev); \
512 } while (false)
513 #else
514 #define UART_CC13XX_CC26XX_POWER_UART(n) \
515 do { \
516 uint32_t domain, periph; \
517 \
518 /* Enable UART power domain */ \
519 if (DT_INST_REG_ADDR(n) == 0x40001000) { \
520 domain = PRCM_DOMAIN_SERIAL; \
521 periph = PRCM_PERIPH_UART0; \
522 } else { \
523 domain = PRCM_DOMAIN_PERIPH; \
524 periph = PRCM_PERIPH_UART1; \
525 } \
526 PRCMPowerDomainOn(domain); \
527 \
528 /* Enable UART peripherals */ \
529 PRCMPeripheralRunEnable(periph); \
530 PRCMPeripheralSleepEnable(periph); \
531 \
532 /* Load PRCM settings */ \
533 PRCMLoadSet(); \
534 while (!PRCMLoadGet()) { \
535 continue; \
536 } \
537 \
538 /* UART should not be accessed until power domain is on. */ \
539 while (PRCMPowerDomainsAllOn(domain) != \
540 PRCM_DOMAIN_POWER_ON) { \
541 continue; \
542 } \
543 } while (false)
544 #endif
545
546 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
547 #define UART_CC13XX_CC26XX_IRQ_CFG(n) \
548 do { \
549 const struct uart_cc13xx_cc26xx_config *config = \
550 dev->config; \
551 \
552 UARTIntClear(config->reg, UART_INT_RX); \
553 \
554 IRQ_CONNECT(DT_INST_IRQN(n), \
555 DT_INST_IRQ(n, priority), \
556 uart_cc13xx_cc26xx_isr, \
557 DEVICE_DT_INST_GET(n), \
558 0); \
559 irq_enable(DT_INST_IRQN(n)); \
560 /* Causes an initial TX ready INT when TX INT enabled */\
561 UARTCharPutNonBlocking(config->reg, '\0'); \
562 } while (false)
563
564 #define UART_CC13XX_CC26XX_INT_FIELDS \
565 .callback = NULL, \
566 .user_data = NULL,
567 #else
568 #define UART_CC13XX_CC26XX_IRQ_CFG(n)
569 #define UART_CC13XX_CC26XX_INT_FIELDS
570 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
571
572 #define UART_CC13XX_CC26XX_DEVICE_DEFINE(n) \
573 PM_DEVICE_DT_INST_DEFINE(n, uart_cc13xx_cc26xx_pm_action); \
574 \
575 DEVICE_DT_INST_DEFINE(n, \
576 uart_cc13xx_cc26xx_init_##n, \
577 PM_DEVICE_DT_INST_GET(n), \
578 &uart_cc13xx_cc26xx_data_##n, &uart_cc13xx_cc26xx_config_##n,\
579 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
580 &uart_cc13xx_cc26xx_driver_api)
581
582 #define UART_CC13XX_CC26XX_INIT_FUNC(n) \
583 static int uart_cc13xx_cc26xx_init_##n(const struct device *dev) \
584 { \
585 struct uart_cc13xx_cc26xx_data *data = dev->data; \
586 int ret; \
587 \
588 UART_CC13XX_CC26XX_POWER_UART(n); \
589 \
590 ret = pinctrl_apply_state(data->pcfg, PINCTRL_STATE_DEFAULT); \
591 if (ret < 0) { \
592 return ret; \
593 } \
594 \
595 /* Configure and enable UART */ \
596 ret = uart_cc13xx_cc26xx_configure(dev, &data->uart_config);\
597 \
598 /* Enable interrupts */ \
599 UART_CC13XX_CC26XX_IRQ_CFG(n); \
600 \
601 return ret; \
602 }
603
604
605 #define UART_CC13XX_CC26XX_INIT(n) \
606 PINCTRL_DT_INST_DEFINE(n); \
607 UART_CC13XX_CC26XX_INIT_FUNC(n); \
608 \
609 static const struct uart_cc13xx_cc26xx_config \
610 uart_cc13xx_cc26xx_config_##n = { \
611 .reg = DT_INST_REG_ADDR(n), \
612 .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, \
613 clock_frequency) \
614 }; \
615 \
616 static struct uart_cc13xx_cc26xx_data \
617 uart_cc13xx_cc26xx_data_##n = { \
618 .uart_config = { \
619 .baudrate = DT_INST_PROP(n, current_speed), \
620 .parity = UART_CFG_PARITY_NONE, \
621 .stop_bits = UART_CFG_STOP_BITS_1, \
622 .data_bits = UART_CFG_DATA_BITS_8, \
623 .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
624 }, \
625 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
626 UART_CC13XX_CC26XX_INT_FIELDS \
627 }; \
628 \
629 UART_CC13XX_CC26XX_DEVICE_DEFINE(n);
630
631 DT_INST_FOREACH_STATUS_OKAY(UART_CC13XX_CC26XX_INIT)
632
