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/Zephyr-Core-3.6.0/scripts/tests/twister/
Dtest_quarantine.py235 simulation, argument
266 simulation=simulation
273 simulation=simulation
/Zephyr-Core-3.6.0/boards/posix/native_sim/
DKconfig.board5 bool "Native simulation, 32-bit mode"
12 bool "Native simulation, 64-bit mode"
/Zephyr-Core-3.6.0/tests/bsim/
DREADME.md2 simulation, and therefore cannot be run directly from twister.
55 the required simulated devices and physical layer simulation with the required command line
63 Each test must have a unique simulation id, to enable running different tests in parallel.
77 pairing, powering off, and powering up after as a new simulation,
78 they should strive for using separate simulation ids for each simulation part,
79 in that way ensuring that the simulation radio activity of each segment can be inspected a
/Zephyr-Core-3.6.0/scripts/pylib/twister/twisterlib/
Dquarantine.py29 def get_matched_quarantine(self, testname, platform, architecture, simulation): argument
30 qelem = self.quarantine.get_matched_quarantine(testname, platform, architecture, simulation)
109 simulation: str) -> QuarantineElement | None:
123 … and (matched := _is_element_matched(simulation, qelem.re_simulations)) is False):
Dtestinstance.py179 elif self.platform.simulation != "na":
180 if self.platform.simulation == "qemu":
185 handler = SimulationHandler(self, self.platform.simulation)
208 if os.name == 'nt' and self.platform.simulation != 'na':
222 (self.platform.simulation in SUPPORTED_SIMS and \
223 self.platform.simulation not in self.testsuite.simulation_exclude) or \
228 … target_ready = bool(filter == 'runnable' or self.platform.simulation in SUPPORTED_SIMS_IN_PYTEST)
232 self.platform.simulation in SUPPORTED_SIMS_WITH_EXEC and \
Dplatform.py42 self.simulation = "na"
75 self.simulation = data.get('simulation', "na")
/Zephyr-Core-3.6.0/boards/posix/nrf_bsim/doc/
Dnrf52_bsim.rst116 option indicates you want to run it detached from a BabbleSim simulation. This
120 When you want to run a simulation with radio activity you need to run also the
121 BableSim 2G4 (2.4GHz) physical layer simulation (phy).
154 And then run them together with BabbleSim's 2G4 physical layer simulation:
164 this simulation; the ``-D`` option tells the Phy how many devices will be run
165 in this simulation; the ``-d`` option tells each device which is its device
166 number in the simulation; and the ``-sim_length`` option specifies the length
167 of the simulation in microseconds.
200 breakpoint will pause the whole simulation.
213 If for some reason you want to limit the speed of the simulation to real
/Zephyr-Core-3.6.0/boards/arm64/fvp_base_revc_2xaemv8a/
DKconfig.board5 bool "FVP Base RevC AEMv8A simulation board"
/Zephyr-Core-3.6.0/boards/arm64/fvp_baser_aemv8r/
DKconfig.board5 bool "FVP BaseR AEMv8R simulation board"
/Zephyr-Core-3.6.0/boards/arm/fvp_baser_aemv8r_aarch32/
DKconfig.board6 bool "FVP BaseR AEMv8R AArch32 simulation board"
/Zephyr-Core-3.6.0/soc/arm64/arm/fvp_aemv8a/
DKconfig.soc9 bool "ARM FVP Base RevC 2xAEMv8A AArch64 simulation"
/Zephyr-Core-3.6.0/soc/arm/arm/fvp_aemv8r_aarch32/
DKconfig.soc9 bool "ARM FVP AEMv8R aarch32 simulation"
/Zephyr-Core-3.6.0/soc/arc/snps_nsim/
DKconfig.defconfig.hs6x_smp18 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
DKconfig.defconfig.hs_smp22 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
/Zephyr-Core-3.6.0/boards/arm/fvp_baser_aemv8r_aarch32/doc/
Dindex.rst21 To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
99 .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-e…
102 .. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs
/Zephyr-Core-3.6.0/soc/arm64/arm/fvp_aemv8r/
DKconfig.soc9 bool "ARM FVP AEMv8R aarch64 simulation"
/Zephyr-Core-3.6.0/boards/posix/doc/
Dbsim_boards_design.rst24 simulation boards, including how to use them,
50 integration testing of embedded code on workstation/simulation.
87 As such can provide better integration coverage than simulation ins ome cases,
91 They otherwise serve a very similar purpose to simulation integration tests.
97 - Using bsim boards with the BabbleSim Physical layer simulation allows
134 simulation specific ones.
143 - The SOC `inf_clock` layer provides an adaptation to the native simulator CPU "simulation"
144 and the handling of control between the "CPU simulation" (Zephyr threads) and the
207 In general simulation time will pass much faster than real time,
208 and the simulation results will not be affected in any way by the
[all …]
/Zephyr-Core-3.6.0/boards/arm64/fvp_baser_aemv8r/doc/
Dindex.rst26 To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
109 .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-e…
112 .. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs
/Zephyr-Core-3.6.0/doc/develop/test/
Dbsim.rst18 When there is radio activity, this Linux executable will connect to the BabbleSim Phy simulation
35 necessary to connect them to a physical layer simulation. Thanks to this, these target boards can
42 When there is radio activity, BabbleSim tests require at the very least a physical layer simulation
/Zephyr-Core-3.6.0/boards/posix/nrf_bsim/
DKconfig.board4 bool "NRF52 simulation model"
/Zephyr-Core-3.6.0/boards/riscv/opentitan_earlgrey/doc/
Dindex.rst33 the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
69 in simulated flash. The OpenTitan test ROM will then run in simulation, read
/Zephyr-Core-3.6.0/soc/nios2/nios2f-zephyr/cpu/
Dghrd_10m50da.qpf7 # (including device programming or simulation files), and any
/Zephyr-Core-3.6.0/boards/arm/mps3_an547/doc/
Dindex.rst26 The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the
29 simulation since it provides access to the Ethos-U55 NPU, which is unavailable
30 in QEMU or other simulation platforms.
32 To run the Fixed Virtual Platform simulation tool you must download "FVP model
/Zephyr-Core-3.6.0/boards/xtensa/qemu_xtensa/doc/
Dindex.rst10 configuration provides support for the Xtensa simulation environment.
/Zephyr-Core-3.6.0/drivers/flash/
DKconfig.simulator32 bool "Hardware timing simulation"

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