1# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_NSIM_HS_SMP
5
6config CPU_HS3X
7	default y
8
9config NUM_IRQ_PRIO_LEVELS
10	# This processor supports 16 priority levels:
11	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
12	default 2
13
14config NUM_IRQS
15	# must be > the highest interrupt number used
16	default 88
17
18config RGF_NUM_BANKS
19	default 2
20
21config SYS_CLOCK_HW_CYCLES_PER_SEC
22        # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
23	default 1000000
24
25config ARC_FIRQ
26	default y
27
28config CACHE_MANAGEMENT
29	default y
30
31config ARC_CONNECT
32	default y
33
34config MP_MAX_NUM_CPUS
35	default 2
36
37endif # SOC_NSIM_HS_SMP
38