Searched refs:bus_clk (Results 1 – 21 of 21) sorted by relevance
| /Zephyr-Core-3.4.0/drivers/counter/ |
| D | counter_ll_stm32_timer.c | 384 uint32_t bus_clk, apb_psc; in counter_stm32_get_tim_clk() local
393 &bus_clk); in counter_stm32_get_tim_clk()
437 *tim_clk = bus_clk * 2u; in counter_stm32_get_tim_clk()
447 *tim_clk = bus_clk * 4u; in counter_stm32_get_tim_clk()
458 *tim_clk = bus_clk; in counter_stm32_get_tim_clk()
460 *tim_clk = bus_clk * 2u; in counter_stm32_get_tim_clk()
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| /Zephyr-Core-3.4.0/drivers/pwm/ |
| D | pwm_stm32.c | 157 uint32_t bus_clk, apb_psc; in get_tim_clk() local
162 &bus_clk); in get_tim_clk()
207 *tim_clk = bus_clk * 2u; in get_tim_clk()
217 *tim_clk = bus_clk * 4u; in get_tim_clk()
228 *tim_clk = bus_clk; in get_tim_clk()
230 *tim_clk = bus_clk * 2u; in get_tim_clk()
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/k2x/ |
| D | soc.c | 66 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/kv5x/ |
| D | soc.c | 60 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/k8x/ |
| D | soc.c | 64 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/kwx/ |
| D | soc_kw2xd.c | 68 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/k6x/ |
| D | soc.c | 71 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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| /Zephyr-Core-3.4.0/drivers/i2c/ |
| D | i2c_mchp_xec.c | 41 uint32_t bus_clk; member
80 .bus_clk = 0x00004F4F,
87 .bus_clk = 0x00000F17,
94 .bus_clk = 0x00000509,
128 MCHP_I2C_SMB_BUS_CLK(ba) = xec_cfg_params[data->speed_id].bus_clk; in i2c_xec_reset_config()
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| D | i2c_mchp_xec_v2.c | 79 uint32_t bus_clk; member
119 .bus_clk = 0x00004F4F,
126 .bus_clk = 0x00000F17,
133 .bus_clk = 0x00000509,
265 regs->BUSCLK = xec_cfg_params[data->speed_id].bus_clk; in i2c_xec_reset_config()
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| /Zephyr-Core-3.4.0/drivers/serial/ |
| D | uart_rcar.c | 23 struct rcar_cpg_clk bus_clk; member
288 (clock_control_subsys_t)&config->bus_clk, in uart_rcar_init()
545 .bus_clk.module = \
547 .bus_clk.domain = \
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| /Zephyr-Core-3.4.0/boards/arm/ip_k66f/ |
| D | ip_k66f.dts | 51 bus_clk {
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/ke1xf/ |
| D | soc.c | 37 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(bus_clk), 1, 16,
49 .divBus = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(bus_clk)),
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| /Zephyr-Core-3.4.0/drivers/can/ |
| D | can_rcar.c | 174 struct rcar_cpg_clk bus_clk; member
1039 (clock_control_subsys_t)&config->bus_clk); in can_rcar_init()
1132 *rate = config->bus_clk.rate; in can_rcar_get_core_clock()
1198 .bus_clk.module = \
1200 .bus_clk.domain = \
1202 .bus_clk.rate = 40000000, \
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| /Zephyr-Core-3.4.0/drivers/sdhc/ |
| D | imx_usdhc.c | 246 uint32_t src_clk_hz, bus_clk; in imx_usdhc_set_io() local
270 bus_clk = USDHC_SetSdClock(cfg->base, src_clk_hz, ios->clock); in imx_usdhc_set_io()
271 LOG_DBG("BUS CLOCK: %d", bus_clk); in imx_usdhc_set_io()
272 if (bus_clk == 0) { in imx_usdhc_set_io()
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| /Zephyr-Core-3.4.0/dts/arm/nxp/ |
| D | nxp_ke1xf.dtsi | 170 bus_clk: bus_clk { label
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| D | nxp_kv5x.dtsi | 55 bus_clk {
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| D | nxp_kw2xd.dtsi | 93 bus_clk {
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| D | nxp_k8x.dtsi | 60 bus_clk {
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| D | nxp_k2x.dtsi | 94 bus_clk {
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| D | nxp_k6x.dtsi | 124 bus_clk {
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| /Zephyr-Core-3.4.0/boards/arm/twr_ke18f/ |
| D | twr_ke18f.dts | 176 bus_clk {
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