1/* 2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/kinetis_pcc.h> 10#include <zephyr/dt-bindings/clock/kinetis_scg.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13 14/ { 15 aliases { 16 watchdog0 = &wdog; 17 }; 18 19 chosen { 20 zephyr,flash-controller = &ftfe; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-m4f"; 30 reg = <0>; 31 }; 32 }; 33 34 power-states { 35 idle: idle { 36 compatible = "zephyr,power-state"; 37 power-state-name = "runtime-idle"; 38 }; 39 40 stop: stop { 41 compatible = "zephyr,power-state"; 42 power-state-name = "suspend-to-idle"; 43 substate-id = <0>; 44 }; 45 46 pstop1: pstop1 { 47 compatible = "zephyr,power-state"; 48 power-state-name = "suspend-to-idle"; 49 substate-id = <1>; 50 }; 51 52 pstop2: pstop2 { 53 compatible = "zephyr,power-state"; 54 power-state-name = "suspend-to-idle"; 55 substate-id = <2>; 56 }; 57 }; 58 59 temp0: temp0 { 60 compatible = "nxp,kinetis-temperature"; 61 io-channels = <&adc0 26>, <&adc0 27>; 62 io-channel-names = "SENSOR", "BANDGAP"; 63 bandgap-voltage = <1000000>; 64 vtemp25 = <740500>; 65 sensor-slope-cold = <1564>; 66 sensor-slope-hot = <1564>; 67 status = "disabled"; 68 }; 69 70 temp1: temp1 { 71 compatible = "nxp,kinetis-temperature"; 72 io-channels = <&adc1 26>, <&adc1 27>; 73 io-channel-names = "SENSOR", "BANDGAP"; 74 bandgap-voltage = <1000000>; 75 vtemp25 = <740500>; 76 sensor-slope-cold = <1564>; 77 sensor-slope-hot = <1564>; 78 status = "disabled"; 79 }; 80 81 temp2: temp2 { 82 compatible = "nxp,kinetis-temperature"; 83 io-channels = <&adc2 26>, <&adc2 27>; 84 io-channel-names = "SENSOR", "BANDGAP"; 85 bandgap-voltage = <1000000>; 86 vtemp25 = <740500>; 87 sensor-slope-cold = <1564>; 88 sensor-slope-hot = <1564>; 89 status = "disabled"; 90 }; 91 92 /* Dummy pinctrl node, filled with pin mux options at board level */ 93 pinctrl: pinctrl { 94 compatible = "nxp,kinetis-pinctrl"; 95 status = "okay"; 96 }; 97 98 soc { 99 edma: dma-controller@40008000 { 100 compatible = "nxp,mcux-edma"; 101 dma-channels = <16>; 102 dma-requests = <64>; 103 nxp,mem2mem; 104 reg = <0x40008000 0x1000>, <0x40021000 0x1000>; 105 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 106 <4 0>, <5 0>, <6 0>, <7 0>, 107 <8 0>, <9 0>, <10 0>, <11 0>, 108 <12 0>, <13 0>, <14 0>, <15 0>, 109 <16 0>; 110 status = "disabled"; 111 #dma-cells = <2>; 112 }; 113 114 mpu: mpu@4000d000 { 115 compatible = "nxp,kinetis-mpu"; 116 reg = <0x4000d000 0x1000>; 117 status = "disabled"; 118 }; 119 120 sim: sim@40048000 { 121 compatible = "nxp,kinetis-ke1xf-sim"; 122 reg = <0x40048000 0x1000>; 123 }; 124 125 scg: scg@40064000 { 126 compatible = "nxp,kinetis-scg"; 127 reg = <0x40064000 0x1000>; 128 #clock-cells = <1>; 129 130 sosc_clk: sosc_clk { 131 compatible = "fixed-clock"; 132 status = "disabled"; 133 #clock-cells = <0>; 134 }; 135 136 sirc_clk: sirc_clk { 137 compatible = "fixed-clock"; 138 clock-frequency = <8000000>; 139 #clock-cells = <0>; 140 }; 141 142 firc_clk: firc_clk { 143 compatible = "fixed-clock"; 144 clock-frequency = <48000000>; 145 #clock-cells = <0>; 146 }; 147 148 pll: pll { 149 compatible = "fixed-factor-clock"; 150 clocks = <&sosc_clk>; 151 clock-div = <1>; 152 clock-mult = <16>; 153 #clock-cells = <0>; 154 }; 155 156 spll_clk: spll_clk { 157 compatible = "fixed-factor-clock"; 158 clocks = <&pll>; 159 clock-div = <2>; 160 #clock-cells = <0>; 161 }; 162 163 core_clk: core_clk { 164 compatible = "fixed-factor-clock"; 165 clocks = <&firc_clk>; 166 clock-div = <1>; 167 #clock-cells = <0>; 168 }; 169 170 bus_clk: bus_clk { 171 compatible = "fixed-factor-clock"; 172 clocks = <&core_clk>; 173 clock-div = <1>; 174 #clock-cells = <0>; 175 }; 176 177 slow_clk: slow_clk { 178 compatible = "fixed-factor-clock"; 179 clocks = <&core_clk>; 180 clock-div = <2>; 181 #clock-cells = <0>; 182 }; 183 184 clkout_clk: clkout_clk { 185 compatible = "fixed-factor-clock"; 186 status = "disabled"; 187 clocks = <&firc_clk>; 188 #clock-cells = <0>; 189 }; 190 191 splldiv1_clk: splldiv1_clk { 192 compatible = "fixed-factor-clock"; 193 clocks = <&spll_clk>; 194 clock-div = <0>; 195 #clock-cells = <0>; 196 }; 197 198 splldiv2_clk: splldiv2_clk { 199 compatible = "fixed-factor-clock"; 200 clocks = <&spll_clk>; 201 clock-div = <0>; 202 #clock-cells = <0>; 203 }; 204 205 sircdiv1_clk: sircdiv1_clk { 206 compatible = "fixed-factor-clock"; 207 clocks = <&sirc_clk>; 208 clock-div = <0>; 209 #clock-cells = <0>; 210 }; 211 212 sircdiv2_clk: sircdiv2_clk { 213 compatible = "fixed-factor-clock"; 214 clocks = <&sirc_clk>; 215 clock-div = <0>; 216 #clock-cells = <0>; 217 }; 218 219 fircdiv1_clk: fircdiv1_clk { 220 compatible = "fixed-factor-clock"; 221 clocks = <&firc_clk>; 222 clock-div = <0>; 223 #clock-cells = <0>; 224 }; 225 226 fircdiv2_clk: fircdiv2_clk { 227 compatible = "fixed-factor-clock"; 228 clocks = <&firc_clk>; 229 clock-div = <0>; 230 #clock-cells = <0>; 231 }; 232 233 soscdiv1_clk: soscdiv1_clk { 234 compatible = "fixed-factor-clock"; 235 clocks = <&sosc_clk>; 236 clock-div = <0>; 237 #clock-cells = <0>; 238 }; 239 240 soscdiv2_clk: soscdiv2_clk { 241 compatible = "fixed-factor-clock"; 242 clocks = <&sosc_clk>; 243 clock-div = <0>; 244 #clock-cells = <0>; 245 }; 246 }; 247 248 pmc: pmc@4007d000 { 249 reg = <0x4007d000 0x1000>; 250 251 lpo: lpo128k { 252 /* LPO clock */ 253 compatible = "fixed-clock"; 254 clock-frequency = <128000>; 255 #clock-cells = <0>; 256 }; 257 }; 258 259 pcc: pcc@40065000 { 260 compatible = "nxp,kinetis-pcc"; 261 reg = <0x40065000 0x1000>; 262 #clock-cells = <2>; 263 }; 264 265 rtc: rtc@4003d000 { 266 compatible = "nxp,kinetis-rtc"; 267 reg = <0x4003d000 0x1000>; 268 interrupts = <46 0>, <47 0>; 269 interrupt-names = "alarm", "seconds"; 270 clock-frequency = <32768>; 271 prescaler = <32768>; 272 }; 273 274 dac0: dac@4003f000 { 275 compatible = "nxp,kinetis-dac32"; 276 reg = <0x4003f000 0x1000>; 277 interrupts = <56 0>; 278 clocks = <&scg KINETIS_SCG_BUS_CLK>; 279 voltage-reference = <1>; 280 buffered; 281 status = "disabled"; 282 #io-channel-cells = <1>; 283 }; 284 285 lptmr0: lptmr@40040000 { 286 compatible = "nxp,kinetis-lptmr"; 287 reg = <0x40040000 0x1000>; 288 interrupts = <58 0>; 289 clock-frequency = <128000>; 290 prescaler = <1>; 291 clk-source = <1>; 292 }; 293 294 wdog: watchdog@40052000 { 295 compatible = "nxp,kinetis-wdog32"; 296 reg = <0x40052000 0x1000>; 297 interrupts = <22 0>; 298 clocks = <&lpo>; 299 clk-source = <1>; 300 clk-divider = <256>; 301 }; 302 303 pwt: pwt@40056000 { 304 compatible = "nxp,kinetis-pwt"; 305 reg = <0x40056000 0x1000>; 306 interrupts = <29 0>; 307 clocks = <&scg KINETIS_SCG_BUS_CLK>; 308 prescaler = <1>; 309 status = "disabled"; 310 311 #pwm-cells = <3>; 312 }; 313 314 ftfe: flash-controller@40020000 { 315 compatible = "nxp,kinetis-ftfe"; 316 reg = <0x40020000 0x1000>; 317 interrupts = <18 0>, <19 0>; 318 interrupt-names = "command-complete", "read-collision"; 319 320 #address-cells = <1>; 321 #size-cells = <1>; 322 }; 323 324 lpuart0: uart@4006a000 { 325 compatible = "nxp,kinetis-lpuart"; 326 reg = <0x4006a000 0x1000>; 327 interrupts = <31 0>, <32 0>; 328 interrupt-names = "transmit", "receive"; 329 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>; 330 dmas = <&edma 1 2>, <&edma 2 3>; 331 dma-names = "rx", "tx"; 332 status = "disabled"; 333 }; 334 335 lpuart1: uart@4006b000 { 336 compatible = "nxp,kinetis-lpuart"; 337 reg = <0x4006b000 0x1000>; 338 interrupts = <33 0>, <34 0>; 339 interrupt-names = "transmit", "receive"; 340 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>; 341 dmas = <&edma 3 4>, <&edma 4 5>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 lpuart2: uart@4006c000 { 347 compatible = "nxp,kinetis-lpuart"; 348 reg = <0x4006c000 0x1000>; 349 interrupts = <35 0>, <36 0>; 350 interrupt-names = "transmit", "receive"; 351 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>; 352 dmas = <&edma 5 6>, <&edma 5 7>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 }; 356 357 lpi2c0: i2c@40066000 { 358 compatible = "nxp,imx-lpi2c"; 359 clock-frequency = <I2C_BITRATE_STANDARD>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <0x40066000 0x1000>; 363 interrupts = <24 0>; 364 clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>; 365 status = "disabled"; 366 }; 367 368 lpi2c1: i2c@40067000 { 369 compatible = "nxp,imx-lpi2c"; 370 clock-frequency = <I2C_BITRATE_STANDARD>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0x40067000 0x1000>; 374 interrupts = <25 0>; 375 clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>; 376 status = "disabled"; 377 }; 378 379 lpspi0: spi@4002c000 { 380 compatible = "nxp,imx-lpspi"; 381 reg = <0x4002c000 0x1000>; 382 interrupts = <26 0>; 383 clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>; 384 status = "disabled"; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 }; 388 389 lpspi1: spi@4002d000 { 390 compatible = "nxp,imx-lpspi"; 391 reg = <0x4002d000 0x1000>; 392 interrupts = <27 0>; 393 clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>; 394 status = "disabled"; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 }; 398 399 flexcan0: can@40024000 { 400 compatible = "nxp,flexcan"; 401 reg = <0x40024000 0x1000>; 402 interrupts = <78 0>, <79 0>, <80 0>, <81 0>; 403 interrupt-names = "warning", "error", "wake-up", 404 "mb-0-15"; 405 clocks = <&scg KINETIS_SCG_BUS_CLK>; 406 clk-source = <1>; 407 sjw = <1>; 408 sample-point = <875>; 409 status = "disabled"; 410 }; 411 412 flexcan1: can@40025000 { 413 compatible = "nxp,flexcan"; 414 reg = <0x40025000 0x1000>; 415 interrupts = <85 0>, <86 0>, <87 0>, <88 0>; 416 interrupt-names = "warning", "error", "wake-up", 417 "mb-0-15"; 418 clocks = <&scg KINETIS_SCG_BUS_CLK>; 419 clk-source = <1>; 420 sjw = <1>; 421 sample-point = <875>; 422 status = "disabled"; 423 }; 424 425 porta: pinmux@40049000 { 426 compatible = "nxp,kinetis-pinmux"; 427 reg = <0x40049000 0x1000>; 428 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; 429 }; 430 431 portb: pinmux@4004a000 { 432 compatible = "nxp,kinetis-pinmux"; 433 reg = <0x4004a000 0x1000>; 434 clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; 435 }; 436 437 portc: pinmux@4004b000 { 438 compatible = "nxp,kinetis-pinmux"; 439 reg = <0x4004b000 0x1000>; 440 clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; 441 }; 442 443 portd: pinmux@4004c000 { 444 compatible = "nxp,kinetis-pinmux"; 445 reg = <0x4004c000 0x1000>; 446 clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; 447 }; 448 449 porte: pinmux@4004d000 { 450 compatible = "nxp,kinetis-pinmux"; 451 reg = <0x4004d000 0x1000>; 452 clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; 453 }; 454 455 gpioa: gpio@400ff000 { 456 compatible = "nxp,kinetis-gpio"; 457 status = "disabled"; 458 reg = <0x400ff000 0x40>; 459 interrupts = <59 2>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 nxp,kinetis-port = <&porta>; 463 }; 464 465 gpiob: gpio@400ff040 { 466 compatible = "nxp,kinetis-gpio"; 467 status = "disabled"; 468 reg = <0x400ff040 0x40>; 469 interrupts = <60 2>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 nxp,kinetis-port = <&portb>; 473 }; 474 475 gpioc: gpio@400ff080 { 476 compatible = "nxp,kinetis-gpio"; 477 status = "disabled"; 478 reg = <0x400ff080 0x40>; 479 interrupts = <61 2>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 nxp,kinetis-port = <&portc>; 483 }; 484 485 gpiod: gpio@400ff0c0 { 486 compatible = "nxp,kinetis-gpio"; 487 status = "disabled"; 488 reg = <0x400ff0c0 0x40>; 489 interrupts = <62 2>; 490 gpio-controller; 491 #gpio-cells = <2>; 492 nxp,kinetis-port = <&portd>; 493 }; 494 495 gpioe: gpio@400ff100 { 496 compatible = "nxp,kinetis-gpio"; 497 status = "disabled"; 498 reg = <0x400ff100 0x40>; 499 interrupts = <63 2>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 nxp,kinetis-port = <&porte>; 503 }; 504 505 adc0: adc@4003b000 { 506 compatible = "nxp,kinetis-adc12"; 507 reg = <0x4003b000 0x1000>; 508 interrupts = <39 0>; 509 clocks = <&pcc 0xec KINETIS_PCC_SRC_FIRC_ASYNC>; 510 clk-source = <0>; 511 clk-divider = <1>; 512 status = "disabled"; 513 #io-channel-cells = <1>; 514 }; 515 516 adc1: adc@40027000 { 517 compatible = "nxp,kinetis-adc12"; 518 reg = <0x40027000 0x1000>; 519 interrupts = <73 0>; 520 clocks = <&pcc 0x9c KINETIS_PCC_SRC_FIRC_ASYNC>; 521 clk-source = <0>; 522 clk-divider = <1>; 523 status = "disabled"; 524 #io-channel-cells = <1>; 525 }; 526 527 adc2: adc@4003c000 { 528 compatible = "nxp,kinetis-adc12"; 529 reg = <0x4003c000 0x1000>; 530 interrupts = <74 0>; 531 clocks = <&pcc 0xf0 KINETIS_PCC_SRC_FIRC_ASYNC>; 532 clk-source = <0>; 533 clk-divider = <1>; 534 status = "disabled"; 535 #io-channel-cells = <1>; 536 }; 537 538 ftm0: ftm@40038000 { 539 compatible = "nxp,kinetis-ftm"; 540 reg = <0x40038000 0x1000>; 541 interrupts = <42 0>; 542 clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>; 543 prescaler = <16>; 544 status = "disabled"; 545 }; 546 547 ftm1: ftm@40039000 { 548 compatible = "nxp,kinetis-ftm"; 549 reg = <0x40039000 0x1000>; 550 interrupts = <43 0>; 551 clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>; 552 prescaler = <16>; 553 status = "disabled"; 554 }; 555 556 ftm2: ftm@4003a000 { 557 compatible = "nxp,kinetis-ftm"; 558 reg = <0x4003a000 0x1000>; 559 interrupts = <44 0>; 560 clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>; 561 prescaler = <16>; 562 status = "disabled"; 563 }; 564 565 ftm3: ftm@40026000 { 566 compatible = "nxp,kinetis-ftm"; 567 reg = <0x40026000 0x1000>; 568 interrupts = <71 0>; 569 clocks = <&pcc 0x98 KINETIS_PCC_SRC_FIRC_ASYNC>; 570 prescaler = <16>; 571 status = "disabled"; 572 }; 573 574 cmp0: cmp@40073000 { 575 compatible = "nxp,kinetis-acmp"; 576 reg = <0x40073000 0x1000>; 577 interrupts = <40 0>; 578 clocks = <&scg KINETIS_SCG_BUS_CLK>; 579 status = "disabled"; 580 #io-channel-cells = <2>; 581 }; 582 583 cmp1: cmp@40074000 { 584 compatible = "nxp,kinetis-acmp"; 585 reg = <0x40074000 0x1000>; 586 interrupts = <41 0>; 587 clocks = <&scg KINETIS_SCG_BUS_CLK>; 588 status = "disabled"; 589 #io-channel-cells = <2>; 590 }; 591 592 cmp2: cmp@40075000 { 593 compatible = "nxp,kinetis-acmp"; 594 reg = <0x40075000 0x1000>; 595 interrupts = <70 0>; 596 clocks = <&scg KINETIS_SCG_BUS_CLK>; 597 status = "disabled"; 598 #io-channel-cells = <2>; 599 }; 600 }; 601}; 602 603&nvic { 604 arm,num-irq-priority-bits = <4>; 605}; 606
