1 /*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_xec_i2c
8
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
11 #include <zephyr/kernel.h>
12 #include <soc.h>
13 #include <errno.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/drivers/i2c.h>
16 #include <zephyr/drivers/pinctrl.h>
17 #include <zephyr/logging/log.h>
18 #include <zephyr/irq.h>
19 LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
20
21 #define SPEED_100KHZ_BUS 0
22 #define SPEED_400KHZ_BUS 1
23 #define SPEED_1MHZ_BUS 2
24
25 #define EC_OWN_I2C_ADDR 0x7F
26 #define RESET_WAIT_US 20
27 #define BUS_IDLE_US_DFLT 5
28
29 /* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
30 #define WAIT_INTERVAL 50
31 #define WAIT_COUNT 200
32
33 /* Line High Timeout is 2.5 ms (WAIT_LINE_HIGH_USEC * WAIT_LINE_HIGH_COUNT) */
34 #define WAIT_LINE_HIGH_USEC 25
35 #define WAIT_LINE_HIGH_COUNT 100
36
37 /* I2C Read/Write bit pos */
38 #define I2C_READ_WRITE_POS 0
39
40 struct xec_speed_cfg {
41 uint32_t bus_clk;
42 uint32_t data_timing;
43 uint32_t start_hold_time;
44 uint32_t config;
45 uint32_t timeout_scale;
46 };
47
48 struct i2c_xec_config {
49 uint32_t port_sel;
50 uint32_t base_addr;
51 uint8_t girq_id;
52 uint8_t girq_bit;
53 uint8_t pcr_idx;
54 uint8_t pcr_bitpos;
55 struct gpio_dt_spec sda_gpio;
56 struct gpio_dt_spec scl_gpio;
57 const struct pinctrl_dev_config *pcfg;
58 void (*irq_config_func)(void);
59 };
60
61 struct i2c_xec_data {
62 uint32_t pending_stop;
63 uint32_t error_seen;
64 uint32_t timeout_seen;
65 uint32_t previously_in_read;
66 uint32_t speed_id;
67 struct i2c_target_config *slave_cfg;
68 bool slave_attached;
69 bool slave_read;
70 };
71
72 /* Recommended programming values based on 16MHz
73 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
74 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
75 * (16MHz/400KHz -2) = 0x0F + 0x17
76 * (16MHz/1MHz -2) = 0x05 + 0x09
77 */
78 static const struct xec_speed_cfg xec_cfg_params[] = {
79 [SPEED_100KHZ_BUS] = {
80 .bus_clk = 0x00004F4F,
81 .data_timing = 0x0C4D5006,
82 .start_hold_time = 0x0000004D,
83 .config = 0x01FC01ED,
84 .timeout_scale = 0x4B9CC2C7,
85 },
86 [SPEED_400KHZ_BUS] = {
87 .bus_clk = 0x00000F17,
88 .data_timing = 0x040A0A06,
89 .start_hold_time = 0x0000000A,
90 .config = 0x01000050,
91 .timeout_scale = 0x159CC2C7,
92 },
93 [SPEED_1MHZ_BUS] = {
94 .bus_clk = 0x00000509,
95 .data_timing = 0x04060601,
96 .start_hold_time = 0x00000006,
97 .config = 0x10000050,
98 .timeout_scale = 0x089CC2C7,
99 },
100 };
101
i2c_xec_reset_config(const struct device * dev)102 static void i2c_xec_reset_config(const struct device *dev)
103 {
104 const struct i2c_xec_config *config =
105 (const struct i2c_xec_config *const) (dev->config);
106 struct i2c_xec_data *data =
107 (struct i2c_xec_data *const) (dev->data);
108 uint32_t ba = config->base_addr;
109
110 /* Assert RESET */
111 z_mchp_xec_pcr_periph_reset(config->pcr_idx, config->pcr_bitpos);
112 /* Write 0x80. i.e Assert PIN bit, ESO = 0 and Interrupts
113 * disabled (ENI)
114 */
115 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN;
116
117 /* Enable controller and I2C filters */
118 MCHP_I2C_SMB_CFG(ba) = MCHP_I2C_SMB_CFG_GC_EN |
119 MCHP_I2C_SMB_CFG_ENAB |
120 MCHP_I2C_SMB_CFG_FEN |
121 (config->port_sel &
122 MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
123
124 /* Configure bus clock register, Data Timing register,
125 * Repeated Start Hold Time register,
126 * and Timeout Scaling register
127 */
128 MCHP_I2C_SMB_BUS_CLK(ba) = xec_cfg_params[data->speed_id].bus_clk;
129 MCHP_I2C_SMB_DATA_TM(ba) = xec_cfg_params[data->speed_id].data_timing;
130 MCHP_I2C_SMB_RSHT(ba) =
131 xec_cfg_params[data->speed_id].start_hold_time;
132 MCHP_I2C_SMB_TMTSC(ba) = xec_cfg_params[data->speed_id].timeout_scale;
133
134 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
135 MCHP_I2C_SMB_CTRL_ESO |
136 MCHP_I2C_SMB_CTRL_ACK;
137
138 k_busy_wait(RESET_WAIT_US);
139 }
140
xec_spin_yield(int * counter)141 static int xec_spin_yield(int *counter)
142 {
143 *counter = *counter + 1;
144
145 if (*counter > WAIT_COUNT) {
146 return -ETIMEDOUT;
147 }
148
149 k_busy_wait(WAIT_INTERVAL);
150
151 return 0;
152 }
153
cleanup_registers(uint32_t ba)154 static void cleanup_registers(uint32_t ba)
155 {
156 uint32_t cfg = MCHP_I2C_SMB_CFG(ba);
157
158 cfg |= MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
159 MCHP_I2C_SMB_CFG(ba) = cfg;
160 cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
161
162 cfg |= MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
163 MCHP_I2C_SMB_CFG(ba) = cfg;
164 cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
165
166 cfg |= MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
167 MCHP_I2C_SMB_CFG(ba) = cfg;
168 cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
169
170 cfg |= MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
171 MCHP_I2C_SMB_CFG(ba) = cfg;
172 cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
173 }
174
175 #ifdef CONFIG_I2C_TARGET
restart_slave(uint32_t ba)176 static void restart_slave(uint32_t ba)
177 {
178 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
179 MCHP_I2C_SMB_CTRL_ESO |
180 MCHP_I2C_SMB_CTRL_ACK |
181 MCHP_I2C_SMB_CTRL_ENI;
182 }
183 #endif
184
recover_from_error(const struct device * dev)185 static void recover_from_error(const struct device *dev)
186 {
187 const struct i2c_xec_config *config =
188 (const struct i2c_xec_config *const) (dev->config);
189 uint32_t ba = config->base_addr;
190
191 cleanup_registers(ba);
192 i2c_xec_reset_config(dev);
193 }
194
wait_bus_free(const struct device * dev)195 static int wait_bus_free(const struct device *dev)
196 {
197 const struct i2c_xec_config *config =
198 (const struct i2c_xec_config *const) (dev->config);
199 int ret;
200 int counter = 0;
201 uint32_t ba = config->base_addr;
202
203 while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
204 ret = xec_spin_yield(&counter);
205
206 if (ret < 0) {
207 return ret;
208 }
209 }
210
211 /* Check for bus error */
212 if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
213 recover_from_error(dev);
214 return -EBUSY;
215 }
216
217 return 0;
218 }
219
220 /*
221 * Wait with timeout for I2C controller to finish transmit/receive of one
222 * byte(address or data).
223 * When transmit/receive operation is started the I2C PIN status is 1. Upon
224 * normal completion I2C PIN status asserts(0).
225 * We loop checking I2C status for the following events:
226 * Bus Error:
227 * Reset controller and return -EBUSY
228 * Lost Arbitration:
229 * Return -EPERM. We lost bus to another controller. No reset.
230 * PIN == 0: I2C Status LRB is valid and contains ACK/NACK data on 9th clock.
231 * ACK return 0 (success)
232 * NACK Issue STOP, wait for bus minimum idle time, return -EIO.
233 * Timeout:
234 * Reset controller and return -ETIMEDOUT
235 *
236 * NOTE: After generating a STOP the controller will not generate a START until
237 * Bus Minimum Idle time has expired.
238 */
wait_completion(const struct device * dev)239 static int wait_completion(const struct device *dev)
240 {
241 const struct i2c_xec_config *config =
242 (const struct i2c_xec_config *const) (dev->config);
243 int ret;
244 int counter = 0;
245 uint32_t ba = config->base_addr;
246
247 while (1) {
248 uint8_t status = MCHP_I2C_SMB_STS_RO(ba);
249
250 /* Is bus error ? */
251 if (status & MCHP_I2C_SMB_STS_BER) {
252 recover_from_error(dev);
253 return -EBUSY;
254 }
255
256 /* Is Lost arbitration ? */
257 status = MCHP_I2C_SMB_STS_RO(ba);
258 if (status & MCHP_I2C_SMB_STS_LAB) {
259 recover_from_error(dev);
260 return -EPERM;
261 }
262
263 status = MCHP_I2C_SMB_STS_RO(ba);
264 /* PIN -> 0 indicates I2C is done */
265 if (!(status & MCHP_I2C_SMB_STS_PIN)) {
266 /* PIN == 0. LRB contains state of 9th bit */
267 if (status & MCHP_I2C_SMB_STS_LRB_AD0) { /* NACK? */
268 /* Send STOP */
269 MCHP_I2C_SMB_CTRL_WO(ba) =
270 MCHP_I2C_SMB_CTRL_PIN |
271 MCHP_I2C_SMB_CTRL_ESO |
272 MCHP_I2C_SMB_CTRL_STO |
273 MCHP_I2C_SMB_CTRL_ACK;
274 k_busy_wait(BUS_IDLE_US_DFLT);
275 return -EIO;
276 }
277 break; /* success: ACK */
278 }
279
280 ret = xec_spin_yield(&counter);
281 if (ret < 0) {
282 return ret;
283 }
284 }
285
286 return 0;
287 }
288
289 /*
290 * Call GPIO driver to read state of pins.
291 * Return boolean true if both lines HIGH else return boolean false
292 */
check_lines_high(const struct device * dev)293 static bool check_lines_high(const struct device *dev)
294 {
295 const struct i2c_xec_config *config =
296 (const struct i2c_xec_config *const)(dev->config);
297 gpio_port_value_t sda = 0, scl = 0;
298
299 if (gpio_port_get_raw(config->sda_gpio.port, &sda)) {
300 LOG_ERR("gpio_port_get_raw for %s SDA failed", dev->name);
301 return false;
302 }
303
304 /* both pins could be on same GPIO group */
305 if (config->sda_gpio.port == config->scl_gpio.port) {
306 scl = sda;
307 } else {
308 if (gpio_port_get_raw(config->scl_gpio.port, &scl)) {
309 LOG_ERR("gpio_port_get_raw for %s SCL failed",
310 dev->name);
311 return false;
312 }
313 }
314
315 return (sda & BIT(config->sda_gpio.pin)) && (scl & BIT(config->scl_gpio.pin));
316
317 }
318
i2c_xec_configure(const struct device * dev,uint32_t dev_config_raw)319 static int i2c_xec_configure(const struct device *dev,
320 uint32_t dev_config_raw)
321 {
322 struct i2c_xec_data *data =
323 (struct i2c_xec_data *const) (dev->data);
324
325 if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
326 return -ENOTSUP;
327 }
328
329 if (dev_config_raw & I2C_ADDR_10_BITS) {
330 return -ENOTSUP;
331 }
332
333 switch (I2C_SPEED_GET(dev_config_raw)) {
334 case I2C_SPEED_STANDARD:
335 data->speed_id = SPEED_100KHZ_BUS;
336 break;
337 case I2C_SPEED_FAST:
338 data->speed_id = SPEED_400KHZ_BUS;
339 break;
340 case I2C_SPEED_FAST_PLUS:
341 data->speed_id = SPEED_1MHZ_BUS;
342 break;
343 default:
344 return -EINVAL;
345 }
346
347 i2c_xec_reset_config(dev);
348
349 return 0;
350 }
351
i2c_xec_poll_write(const struct device * dev,struct i2c_msg msg,uint16_t addr)352 static int i2c_xec_poll_write(const struct device *dev, struct i2c_msg msg,
353 uint16_t addr)
354 {
355 const struct i2c_xec_config *config =
356 (const struct i2c_xec_config *const) (dev->config);
357 struct i2c_xec_data *data =
358 (struct i2c_xec_data *const) (dev->data);
359 uint32_t ba = config->base_addr;
360 uint8_t i2c_timer = 0, byte;
361 int ret;
362
363 if (data->timeout_seen == 1) {
364 /* Wait to see if the slave has released the CLK */
365 ret = wait_completion(dev);
366 if (ret) {
367 data->timeout_seen = 1;
368 LOG_ERR("%s: %s wait_completion failure %d\n",
369 __func__, dev->name, ret);
370 return ret;
371 }
372 data->timeout_seen = 0;
373
374 /* If we are here, it means the slave has finally released
375 * the CLK. The master needs to end that transaction
376 * gracefully by sending a STOP on the bus.
377 */
378 LOG_DBG("%s: %s Force Stop", __func__, dev->name);
379 MCHP_I2C_SMB_CTRL_WO(ba) =
380 MCHP_I2C_SMB_CTRL_PIN |
381 MCHP_I2C_SMB_CTRL_ESO |
382 MCHP_I2C_SMB_CTRL_STO |
383 MCHP_I2C_SMB_CTRL_ACK;
384 k_busy_wait(BUS_IDLE_US_DFLT);
385 data->pending_stop = 0;
386
387 /* If the timeout had occurred while the master was reading
388 * something from the slave, that read needs to be completed
389 * to clear the bus.
390 */
391 if (data->previously_in_read == 1) {
392 data->previously_in_read = 0;
393 byte = MCHP_I2C_SMB_DATA(ba);
394 }
395 return -EBUSY;
396 }
397
398 if ((data->pending_stop == 0) || (data->error_seen == 1)) {
399 /* Wait till clock and data lines are HIGH */
400 while (check_lines_high(dev) == false) {
401 if (i2c_timer >= WAIT_LINE_HIGH_COUNT) {
402 LOG_DBG("%s: %s not high",
403 __func__, dev->name);
404 data->error_seen = 1;
405 return -EBUSY;
406 }
407 k_busy_wait(WAIT_LINE_HIGH_USEC);
408 i2c_timer++;
409 }
410
411 if (data->error_seen) {
412 LOG_DBG("%s: Recovering %s previously in error",
413 __func__, dev->name);
414 data->error_seen = 0;
415 recover_from_error(dev);
416 }
417
418 /* Wait until bus is free */
419 ret = wait_bus_free(dev);
420 if (ret) {
421 data->error_seen = 1;
422 LOG_DBG("%s: %s wait_bus_free failure %d",
423 __func__, dev->name, ret);
424 return ret;
425 }
426
427 /* Send slave address */
428 MCHP_I2C_SMB_DATA(ba) = (addr & ~BIT(0));
429
430 /* Send start and ack bits */
431 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
432 MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
433 MCHP_I2C_SMB_CTRL_ACK;
434
435 ret = wait_completion(dev);
436 switch (ret) {
437 case 0: /* Success */
438 break;
439
440 case -EIO:
441 LOG_WRN("%s: No Addr ACK from Slave 0x%x on %s",
442 __func__, addr >> 1, dev->name);
443 return ret;
444
445 default:
446 data->error_seen = 1;
447 LOG_ERR("%s: %s wait_comp error %d for addr send",
448 __func__, dev->name, ret);
449 return ret;
450 }
451 }
452
453 /* Send bytes */
454 for (int i = 0U; i < msg.len; i++) {
455 MCHP_I2C_SMB_DATA(ba) = msg.buf[i];
456 ret = wait_completion(dev);
457
458 switch (ret) {
459 case 0: /* Success */
460 break;
461
462 case -EIO:
463 LOG_ERR("%s: No Data ACK from Slave 0x%x on %s",
464 __func__, addr >> 1, dev->name);
465 return ret;
466
467 case -ETIMEDOUT:
468 data->timeout_seen = 1;
469 LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
470 __func__, addr >> 1, dev->name);
471 return ret;
472
473 default:
474 data->error_seen = 1;
475 LOG_ERR("%s: %s wait_completion error %d for data send",
476 __func__, dev->name, ret);
477 return ret;
478 }
479 }
480
481 /* Handle stop bit for last byte to write */
482 if (msg.flags & I2C_MSG_STOP) {
483 /* Send stop and ack bits */
484 MCHP_I2C_SMB_CTRL_WO(ba) =
485 MCHP_I2C_SMB_CTRL_PIN |
486 MCHP_I2C_SMB_CTRL_ESO |
487 MCHP_I2C_SMB_CTRL_STO |
488 MCHP_I2C_SMB_CTRL_ACK;
489 data->pending_stop = 0;
490 } else {
491 data->pending_stop = 1;
492 }
493
494 return 0;
495 }
496
i2c_xec_poll_read(const struct device * dev,struct i2c_msg msg,uint16_t addr)497 static int i2c_xec_poll_read(const struct device *dev, struct i2c_msg msg,
498 uint16_t addr)
499 {
500 const struct i2c_xec_config *config =
501 (const struct i2c_xec_config *const) (dev->config);
502 struct i2c_xec_data *data =
503 (struct i2c_xec_data *const) (dev->data);
504 uint32_t ba = config->base_addr;
505 uint8_t byte, ctrl, i2c_timer = 0;
506 int ret;
507
508 if (data->timeout_seen == 1) {
509 /* Wait to see if the slave has released the CLK */
510 ret = wait_completion(dev);
511 if (ret) {
512 data->timeout_seen = 1;
513 LOG_ERR("%s: %s wait_completion failure %d\n",
514 __func__, dev->name, ret);
515 return ret;
516 }
517 data->timeout_seen = 0;
518
519 /* If we are here, it means the slave has finally released
520 * the CLK. The master needs to end that transaction
521 * gracefully by sending a STOP on the bus.
522 */
523 LOG_DBG("%s: %s Force Stop", __func__, dev->name);
524 MCHP_I2C_SMB_CTRL_WO(ba) =
525 MCHP_I2C_SMB_CTRL_PIN |
526 MCHP_I2C_SMB_CTRL_ESO |
527 MCHP_I2C_SMB_CTRL_STO |
528 MCHP_I2C_SMB_CTRL_ACK;
529 k_busy_wait(BUS_IDLE_US_DFLT);
530 return -EBUSY;
531 }
532
533 if (!(msg.flags & I2C_MSG_RESTART) || (data->error_seen == 1)) {
534 /* Wait till clock and data lines are HIGH */
535 while (check_lines_high(dev) == false) {
536 if (i2c_timer >= WAIT_LINE_HIGH_COUNT) {
537 LOG_DBG("%s: %s not high",
538 __func__, dev->name);
539 data->error_seen = 1;
540 return -EBUSY;
541 }
542 k_busy_wait(WAIT_LINE_HIGH_USEC);
543 i2c_timer++;
544 }
545
546 if (data->error_seen) {
547 LOG_DBG("%s: Recovering %s previously in error",
548 __func__, dev->name);
549 data->error_seen = 0;
550 recover_from_error(dev);
551 }
552
553 /* Wait until bus is free */
554 ret = wait_bus_free(dev);
555 if (ret) {
556 data->error_seen = 1;
557 LOG_DBG("%s: %s wait_bus_free failure %d",
558 __func__, dev->name, ret);
559 return ret;
560 }
561 }
562
563 /* MCHP I2C spec recommends that for repeated start to write to control
564 * register before writing to data register
565 */
566 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO |
567 MCHP_I2C_SMB_CTRL_STA | MCHP_I2C_SMB_CTRL_ACK;
568
569 /* Send slave address */
570 MCHP_I2C_SMB_DATA(ba) = (addr | BIT(0));
571
572 ret = wait_completion(dev);
573 switch (ret) {
574 case 0: /* Success */
575 break;
576
577 case -EIO:
578 data->error_seen = 1;
579 LOG_WRN("%s: No Addr ACK from Slave 0x%x on %s",
580 __func__, addr >> 1, dev->name);
581 return ret;
582
583 case -ETIMEDOUT:
584 data->previously_in_read = 1;
585 data->timeout_seen = 1;
586 LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
587 __func__, addr >> 1, dev->name);
588 return ret;
589
590 default:
591 data->error_seen = 1;
592 LOG_ERR("%s: %s wait_completion error %d for address send",
593 __func__, dev->name, ret);
594 return ret;
595 }
596
597 if (msg.len == 1) {
598 /* Send NACK for last transaction */
599 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
600 }
601
602 /* Read dummy byte */
603 byte = MCHP_I2C_SMB_DATA(ba);
604
605 for (int i = 0U; i < msg.len; i++) {
606 ret = wait_completion(dev);
607 switch (ret) {
608 case 0: /* Success */
609 break;
610
611 case -EIO:
612 LOG_ERR("%s: No Data ACK from Slave 0x%x on %s",
613 __func__, addr >> 1, dev->name);
614 return ret;
615
616 case -ETIMEDOUT:
617 data->previously_in_read = 1;
618 data->timeout_seen = 1;
619 LOG_ERR("%s: Clk stretch Timeout - Slave 0x%x on %s",
620 __func__, addr >> 1, dev->name);
621 return ret;
622
623 default:
624 data->error_seen = 1;
625 LOG_ERR("%s: %s wait_completion error %d for data send",
626 __func__, dev->name, ret);
627 return ret;
628 }
629
630 if (i == (msg.len - 1)) {
631 if (msg.flags & I2C_MSG_STOP) {
632 /* Send stop and ack bits */
633 ctrl = (MCHP_I2C_SMB_CTRL_PIN |
634 MCHP_I2C_SMB_CTRL_ESO |
635 MCHP_I2C_SMB_CTRL_STO |
636 MCHP_I2C_SMB_CTRL_ACK);
637 MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
638 data->pending_stop = 0;
639 }
640 } else if (i == (msg.len - 2)) {
641 /* Send NACK for last transaction */
642 MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
643 }
644 msg.buf[i] = MCHP_I2C_SMB_DATA(ba);
645 }
646
647 return 0;
648 }
649
i2c_xec_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)650 static int i2c_xec_transfer(const struct device *dev, struct i2c_msg *msgs,
651 uint8_t num_msgs, uint16_t addr)
652 {
653 int ret = 0;
654
655 #ifdef CONFIG_I2C_TARGET
656 struct i2c_xec_data *data = dev->data;
657
658 if (data->slave_attached) {
659 LOG_ERR("%s Device is registered as slave", dev->name);
660 return -EBUSY;
661 }
662 #endif
663
664 addr <<= 1;
665 for (int i = 0U; i < num_msgs; i++) {
666 if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
667 ret = i2c_xec_poll_write(dev, msgs[i], addr);
668 if (ret) {
669 LOG_ERR("%s Write error: %d", dev->name, ret);
670 return ret;
671 }
672 } else {
673 ret = i2c_xec_poll_read(dev, msgs[i], addr);
674 if (ret) {
675 LOG_ERR("%s Read error: %d", dev->name, ret);
676 return ret;
677 }
678 }
679 }
680
681 return 0;
682 }
683
i2c_xec_bus_isr(const struct device * dev)684 static void i2c_xec_bus_isr(const struct device *dev)
685 {
686 #ifdef CONFIG_I2C_TARGET
687 const struct i2c_xec_config *config =
688 (const struct i2c_xec_config *const) (dev->config);
689 struct i2c_xec_data *data = dev->data;
690 const struct i2c_target_callbacks *slave_cb = data->slave_cfg->callbacks;
691 uint32_t ba = config->base_addr;
692
693 uint32_t status;
694 uint8_t val;
695
696 uint8_t dummy = 0U;
697
698 if (!data->slave_attached) {
699 return;
700 }
701
702 /* Get current status */
703 status = MCHP_I2C_SMB_STS_RO(ba);
704
705 /* Bus Error */
706 if (status & MCHP_I2C_SMB_STS_BER) {
707 if (slave_cb->stop) {
708 slave_cb->stop(data->slave_cfg);
709 }
710 restart_slave(ba);
711 goto clear_iag;
712 }
713
714 /* External stop */
715 if (status & MCHP_I2C_SMB_STS_EXT_STOP) {
716 if (slave_cb->stop) {
717 slave_cb->stop(data->slave_cfg);
718 }
719 dummy = MCHP_I2C_SMB_DATA(ba);
720 restart_slave(ba);
721 goto clear_iag;
722 }
723
724 /* Address byte handling */
725 if (status & MCHP_I2C_SMB_STS_AAS) {
726 uint8_t slv_data = MCHP_I2C_SMB_DATA(ba);
727
728 if (!(slv_data & BIT(I2C_READ_WRITE_POS))) {
729 /* Slave receive */
730 data->slave_read = false;
731 if (slave_cb->write_requested) {
732 slave_cb->write_requested(data->slave_cfg);
733 }
734 goto clear_iag;
735 } else {
736 /* Slave transmit */
737 data->slave_read = true;
738 if (slave_cb->read_requested) {
739 slave_cb->read_requested(data->slave_cfg, &val);
740 }
741 MCHP_I2C_SMB_DATA(ba) = val;
742 goto clear_iag;
743 }
744 }
745
746 /* Slave transmit */
747 if (data->slave_read) {
748 /* Master has Nacked, then just write a dummy byte */
749 if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_LRB_AD0) {
750 MCHP_I2C_SMB_DATA(ba) = dummy;
751 } else {
752 if (slave_cb->read_processed) {
753 slave_cb->read_processed(data->slave_cfg, &val);
754 }
755 MCHP_I2C_SMB_DATA(ba) = val;
756 }
757 } else {
758 val = MCHP_I2C_SMB_DATA(ba);
759 /* TODO NACK Master */
760 if (slave_cb->write_received) {
761 slave_cb->write_received(data->slave_cfg, val);
762 }
763 }
764
765 clear_iag:
766 MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
767 #endif
768 }
769
770 #ifdef CONFIG_I2C_TARGET
i2c_xec_slave_register(const struct device * dev,struct i2c_target_config * config)771 static int i2c_xec_slave_register(const struct device *dev,
772 struct i2c_target_config *config)
773 {
774 const struct i2c_xec_config *cfg = dev->config;
775 struct i2c_xec_data *data = dev->data;
776 uint32_t ba = cfg->base_addr;
777 int ret;
778 int counter = 0;
779
780 if (!config) {
781 return -EINVAL;
782 }
783
784 if (data->slave_attached) {
785 return -EBUSY;
786 }
787
788 /* Wait for any outstanding transactions to complete so that
789 * the bus is free
790 */
791 while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
792 ret = xec_spin_yield(&counter);
793
794 if (ret < 0) {
795 return ret;
796 }
797 }
798
799 data->slave_cfg = config;
800
801 /* Set own address */
802 MCHP_I2C_SMB_OWN_ADDR(ba) = data->slave_cfg->address;
803 restart_slave(ba);
804
805 data->slave_attached = true;
806
807 /* Clear before enabling girq bit */
808 MCHP_GIRQ_SRC(cfg->girq_id) = BIT(cfg->girq_bit);
809 MCHP_GIRQ_ENSET(cfg->girq_id) = BIT(cfg->girq_bit);
810
811 return 0;
812 }
813
i2c_xec_slave_unregister(const struct device * dev,struct i2c_target_config * config)814 static int i2c_xec_slave_unregister(const struct device *dev,
815 struct i2c_target_config *config)
816 {
817 const struct i2c_xec_config *cfg = dev->config;
818 struct i2c_xec_data *data = dev->data;
819
820 if (!data->slave_attached) {
821 return -EINVAL;
822 }
823
824 data->slave_attached = false;
825
826 MCHP_GIRQ_ENCLR(cfg->girq_id) = BIT(cfg->girq_bit);
827
828 return 0;
829 }
830 #endif
831
832 static const struct i2c_driver_api i2c_xec_driver_api = {
833 .configure = i2c_xec_configure,
834 .transfer = i2c_xec_transfer,
835 #ifdef CONFIG_I2C_TARGET
836 .slave_register = i2c_xec_slave_register,
837 .slave_unregister = i2c_xec_slave_unregister,
838 #endif
839 };
840
i2c_xec_init(const struct device * dev)841 static int i2c_xec_init(const struct device *dev)
842 {
843 const struct i2c_xec_config *cfg = dev->config;
844 struct i2c_xec_data *data =
845 (struct i2c_xec_data *const) (dev->data);
846 int ret;
847
848 data->pending_stop = 0;
849 data->slave_attached = false;
850
851 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
852 if (ret != 0) {
853 LOG_ERR("XEC I2C pinctrl setup failed (%d)", ret);
854 return ret;
855 }
856
857 if (!device_is_ready(cfg->sda_gpio.port)) {
858 LOG_ERR("%s GPIO device is not ready for SDA GPIO", dev->name);
859 return -ENODEV;
860 }
861
862 if (!device_is_ready(cfg->scl_gpio.port)) {
863 LOG_ERR("%s GPIO device is not ready for SCL GPIO", dev->name);
864 return -ENODEV;
865 }
866
867 /* Default configuration */
868 ret = i2c_xec_configure(dev,
869 I2C_MODE_CONTROLLER |
870 I2C_SPEED_SET(I2C_SPEED_STANDARD));
871 if (ret) {
872 LOG_ERR("%s configure failed %d", dev->name, ret);
873 return ret;
874 }
875
876 #ifdef CONFIG_I2C_TARGET
877 const struct i2c_xec_config *config =
878 (const struct i2c_xec_config *const) (dev->config);
879
880 config->irq_config_func();
881 #endif
882 return 0;
883 }
884
885 #define I2C_XEC_DEVICE(n) \
886 \
887 PINCTRL_DT_INST_DEFINE(n); \
888 \
889 static void i2c_xec_irq_config_func_##n(void); \
890 \
891 static struct i2c_xec_data i2c_xec_data_##n; \
892 static const struct i2c_xec_config i2c_xec_config_##n = { \
893 .base_addr = \
894 DT_INST_REG_ADDR(n), \
895 .port_sel = DT_INST_PROP(n, port_sel), \
896 .girq_id = DT_INST_PROP(n, girq), \
897 .girq_bit = DT_INST_PROP(n, girq_bit), \
898 .pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
899 .pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
900 .sda_gpio = GPIO_DT_SPEC_INST_GET(n, sda_gpios), \
901 .scl_gpio = GPIO_DT_SPEC_INST_GET(n, scl_gpios), \
902 .irq_config_func = i2c_xec_irq_config_func_##n, \
903 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
904 }; \
905 I2C_DEVICE_DT_INST_DEFINE(n, i2c_xec_init, NULL, \
906 &i2c_xec_data_##n, &i2c_xec_config_##n, \
907 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
908 &i2c_xec_driver_api); \
909 \
910 static void i2c_xec_irq_config_func_##n(void) \
911 { \
912 IRQ_CONNECT(DT_INST_IRQN(n), \
913 DT_INST_IRQ(n, priority), \
914 i2c_xec_bus_isr, \
915 DEVICE_DT_INST_GET(n), 0); \
916 irq_enable(DT_INST_IRQN(n)); \
917 }
918
919 DT_INST_FOREACH_STATUS_OKAY(I2C_XEC_DEVICE)
920
