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Searched refs:GD32_RESET_USART1 (Results 1 – 16 of 16) sorted by relevance

/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h46 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32vf103.h52 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32l23x.h50 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32a50x.h50 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32f403.h60 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32e10x.h59 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32e50x.h65 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
Dgd32f4xx.h75 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U) macro
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32l23x/
Dgd32l23x.dtsi83 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f3x0.dtsi79 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi107 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi89 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi94 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi80 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f403/
Dgd32f403.dtsi88 resets = <&rctl GD32_RESET_USART1>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi86 resets = <&rctl GD32_RESET_USART1>;