1 /*
2  * Copyright (c) 2022 BrainCo.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
9 
10 #include "gd32-common.h"
11 
12 /**
13  * @name Register offsets
14  * @{
15  */
16 
17 #define GD32_AHB1RST_OFFSET       0x28U
18 #define GD32_APB1RST_OFFSET       0x10U
19 #define GD32_APB2RST_OFFSET       0x0CU
20 
21 /** @} */
22 
23 /**
24  * @name Clock enable/disable definitions for peripherals
25  * @{
26  */
27 
28 /* AHB1 peripherals */
29 #define GD32_RESET_CRC        GD32_RESET_CONFIG(AHB1RST, 6U)
30 #define GD32_RESET_GPIOA      GD32_RESET_CONFIG(AHB1RST, 17U)
31 #define GD32_RESET_GPIOB      GD32_RESET_CONFIG(AHB1RST, 18U)
32 #define GD32_RESET_GPIOC      GD32_RESET_CONFIG(AHB1RST, 19U)
33 #define GD32_RESET_GPIOD      GD32_RESET_CONFIG(AHB1RST, 20U)
34 #define GD32_RESET_GPIOF      GD32_RESET_CONFIG(AHB1RST, 22U)
35 
36 /* AHB2 peripherals */
37 #define GD32_RESET_CAU        GD32_RESET_CONFIG(AHB2RST, 1U)
38 #define GD32_RESET_TRNG       GD32_RESET_CONFIG(AHB2RST, 3U)
39 
40 /* APB1 peripherals */
41 #define GD32_RESET_TIMER1     GD32_RESET_CONFIG(APB1RST, 0U)
42 #define GD32_RESET_TIMER2     GD32_RESET_CONFIG(APB1RST, 1U)
43 #define GD32_RESET_TIMER5     GD32_RESET_CONFIG(APB1RST, 4U)
44 #define GD32_RESET_TIMER6     GD32_RESET_CONFIG(APB1RST, 5U)
45 #define GD32_RESET_TIMER11    GD32_RESET_CONFIG(APB1RST, 8U)
46 #define GD32_RESET_LPTIMER    GD32_RESET_CONFIG(APB1RST, 9U)
47 #define GD32_RESET_SLCD       GD32_RESET_CONFIG(APB1RST, 10U)
48 #define GD32_RESET_WWDGT      GD32_RESET_CONFIG(APB1RST, 11U)
49 #define GD32_RESET_SPI1       GD32_RESET_CONFIG(APB1RST, 14U)
50 #define GD32_RESET_USART1     GD32_RESET_CONFIG(APB1RST, 17U)
51 #define GD32_RESET_LPUART     GD32_RESET_CONFIG(APB1RST, 18U)
52 #define GD32_RESET_UART3      GD32_RESET_CONFIG(APB1RST, 19U)
53 #define GD32_RESET_UART4      GD32_RESET_CONFIG(APB1RST, 20U)
54 #define GD32_RESET_I2C0       GD32_RESET_CONFIG(APB1RST, 21U)
55 #define GD32_RESET_I2C1       GD32_RESET_CONFIG(APB1RST, 22U)
56 #define GD32_RESET_USBD       GD32_RESET_CONFIG(APB1RST, 23U)
57 #define GD32_RESET_I2C2       GD32_RESET_CONFIG(APB1RST, 24U)
58 #define GD32_RESET_PMU        GD32_RESET_CONFIG(APB1RST, 28U)
59 #define GD32_RESET_DAC        GD32_RESET_CONFIG(APB1RST, 29U)
60 #define GD32_RESET_CTC        GD32_RESET_CONFIG(APB1RST, 30U)
61 
62 /* APB2 peripherals */
63 #define GD32_RESET_SYSCFG     GD32_RESET_CONFIG(APB2RST, 0U)
64 #define GD32_RESET_CMP        GD32_RESET_CONFIG(APB2RST, 1U)
65 #define GD32_RESET_ADC        GD32_RESET_CONFIG(APB2RST, 9U)
66 #define GD32_RESET_TIMER8     GD32_RESET_CONFIG(APB2RST, 11U)
67 #define GD32_RESET_SPI0       GD32_RESET_CONFIG(APB2RST, 12U)
68 #define GD32_RESET_USART0     GD32_RESET_CONFIG(APB2RST, 14U)
69 
70 /** @} */
71 
72 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_ */
73