1/*
2 * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32a50x.h>
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-m33f";
23			reg = <0>;
24			#address-cells = <1>;
25			#size-cells = <1>;
26			clock-frequency = <DT_FREQ_M(100)>;
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv8m-mpu";
30				reg = <0xe000ed90 0x40>;
31				arm,num-mpu-regions = <8>;
32			};
33		};
34	};
35
36	soc {
37		sram0: memory@20000000 {
38			compatible = "mmio-sram";
39		};
40
41		rcu: reset-clock-controller@40021000 {
42			compatible = "gd,gd32-rcu";
43			reg = <0x40021000 0x400>;
44			status = "okay";
45
46			cctl: clock-controller {
47				compatible = "gd,gd32-cctl";
48				#clock-cells = <1>;
49				status = "okay";
50			};
51
52			rctl: reset-controller {
53				compatible = "gd,gd32-rctl";
54				#reset-cells = <1>;
55				status = "okay";
56			};
57		};
58
59		fmc: flash-controller@40022000 {
60			compatible = "gd,gd32-flash-controller";
61			reg = <0x40022000 0x400>;
62
63			#address-cells = <1>;
64			#size-cells = <1>;
65
66			flash0: flash@8000000 {
67				compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
68				write-block-size = <2>;
69				max-erase-time-ms = <2578>;
70				bank0-page-size = <DT_SIZE_K(1)>;
71				bank1-page-size = <DT_SIZE_K(1)>;
72			};
73		};
74
75		usart0: usart@40013800 {
76			compatible = "gd,gd32-usart";
77			reg = <0x40013800 0x400>;
78			interrupts = <37 0>;
79			clocks = <&cctl GD32_CLOCK_USART0>;
80			resets = <&rctl GD32_RESET_USART0>;
81			status = "disabled";
82		};
83
84		usart1: usart@40004400 {
85			compatible = "gd,gd32-usart";
86			reg = <0x40004400 0x400>;
87			interrupts = <38 0>;
88			clocks = <&cctl GD32_CLOCK_USART1>;
89			resets = <&rctl GD32_RESET_USART1>;
90			status = "disabled";
91		};
92
93		usart2: usart@40004800 {
94			compatible = "gd,gd32-usart";
95			reg = <0x40004800 0x400>;
96			interrupts = <39 0>;
97			clocks = <&cctl GD32_CLOCK_USART2>;
98			resets = <&rctl GD32_RESET_USART2>;
99			status = "disabled";
100		};
101
102		dac: dac@40007400 {
103			compatible = "gd,gd32-dac";
104			reg = <0x40007400 0x400>;
105			clocks = <&cctl GD32_CLOCK_DAC>;
106			resets = <&rctl GD32_RESET_DAC>;
107			num-channels = <1>;
108			status = "disabled";
109			#io-channel-cells = <1>;
110		};
111
112		i2c0: i2c@40005400 {
113			compatible = "gd,gd32-i2c";
114			reg = <0x40005400 0x400>;
115			#address-cells = <1>;
116			#size-cells = <0>;
117			clock-frequency = <I2C_BITRATE_STANDARD>;
118			interrupts = <31 0>, <32 0>;
119			interrupt-names = "event", "error";
120			clocks = <&cctl GD32_CLOCK_I2C0>;
121			resets = <&rctl GD32_RESET_I2C0>;
122			status = "disabled";
123		};
124
125		i2c1: i2c@40005800 {
126			compatible = "gd,gd32-i2c";
127			reg = <0x40005800 0x400>;
128			#address-cells = <1>;
129			#size-cells = <0>;
130			clock-frequency = <I2C_BITRATE_STANDARD>;
131			interrupts = <33 0>, <34 0>;
132			interrupt-names = "event", "error";
133			clocks = <&cctl GD32_CLOCK_I2C1>;
134			resets = <&rctl GD32_RESET_I2C1>;
135			status = "disabled";
136		};
137
138		spi0: spi@40013000 {
139			compatible = "gd,gd32-spi";
140			reg = <0x40013000 0x400>;
141			interrupts = <35 0>;
142			clocks = <&cctl GD32_CLOCK_SPI0>;
143			resets = <&rctl GD32_RESET_SPI0>;
144			status = "disabled";
145			#address-cells = <1>;
146			#size-cells = <0>;
147		};
148
149		spi1: spi@40003800 {
150			compatible = "gd,gd32-spi";
151			reg = <0x40003800 0x400>;
152			interrupts = <36 0>;
153			clocks = <&cctl GD32_CLOCK_SPI1>;
154			resets = <&rctl GD32_RESET_SPI1>;
155			status = "disabled";
156			#address-cells = <1>;
157			#size-cells = <0>;
158		};
159
160		adc0: adc@40012400 {
161			compatible = "gd,gd32-adc";
162			reg = <0x40012400 0x100>;
163			interrupts = <18 0>;
164			clocks = <&cctl GD32_CLOCK_ADC0>;
165			resets = <&rctl GD32_RESET_ADC0>;
166			channels = <16>;
167			status = "disabled";
168			#io-channel-cells = <1>;
169		};
170
171		adc1: adc@40012800 {
172			compatible = "gd,gd32-adc";
173			reg = <0x40012800 0x100>;
174			interrupts = <18 0>;
175			clocks = <&cctl GD32_CLOCK_ADC1>;
176			resets = <&rctl GD32_RESET_ADC1>;
177			channels = <16>;
178			status = "disabled";
179			#io-channel-cells = <1>;
180		};
181
182		syscfg: syscfg@40010000 {
183			compatible = "gd,gd32-syscfg";
184			reg = <0x40010000 0x400>;
185			clocks = <&cctl GD32_CLOCK_SYSCFG>;
186		};
187
188		exti: interrupt-controller@40010400 {
189			compatible = "gd,gd32-exti";
190			interrupt-controller;
191			#interrupt-cells = <1>;
192			reg = <0x40010400 0x400>;
193			num-lines = <25>;
194			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
195				     <10 0>, <41 0>, <40 0>;
196			interrupt-names = "line0",  "line1", "line2", "line3",
197					  "line4", "line5-9", "line10-15";
198			status = "okay";
199		};
200
201		fwdgt: watchdog@40003000 {
202			compatible = "gd,gd32-fwdgt";
203			reg = <0x40003000 0x400>;
204			status = "disabled";
205		};
206
207		wwdgt: watchdog@40002c00 {
208			compatible = "gd,gd32-wwdgt";
209			reg = <0x40002C00 0x400>;
210			clocks = <&cctl GD32_CLOCK_WWDGT>;
211			resets = <&rctl GD32_RESET_WWDGT>;
212			interrupts = <0 0>;
213			status = "disabled";
214		};
215
216		pinctrl: pin-controller@48000000 {
217			compatible = "gd,gd32-pinctrl-af";
218			reg = <0x48000000 0x1800>;
219			#address-cells = <1>;
220			#size-cells = <1>;
221			status = "okay";
222
223			gpioa: gpio@48000000 {
224				compatible = "gd,gd32-gpio";
225				gpio-controller;
226				#gpio-cells = <2>;
227				reg = <0x48000000 0x400>;
228				clocks = <&cctl GD32_CLOCK_GPIOA>;
229				resets = <&rctl GD32_RESET_GPIOA>;
230				status = "disabled";
231			};
232
233			gpiob: gpio@48000400 {
234				compatible = "gd,gd32-gpio";
235				gpio-controller;
236				#gpio-cells = <2>;
237				reg = <0x48000400 0x400>;
238				clocks = <&cctl GD32_CLOCK_GPIOB>;
239				resets = <&rctl GD32_RESET_GPIOB>;
240				status = "disabled";
241			};
242
243			gpioc: gpio@48000800 {
244				compatible = "gd,gd32-gpio";
245				gpio-controller;
246				#gpio-cells = <2>;
247				reg = <0x48000800 0x400>;
248				clocks = <&cctl GD32_CLOCK_GPIOC>;
249				resets = <&rctl GD32_RESET_GPIOC>;
250				status = "disabled";
251			};
252
253			gpiod: gpio@48000c00 {
254				compatible = "gd,gd32-gpio";
255				gpio-controller;
256				#gpio-cells = <2>;
257				reg = <0x48000c00 0x400>;
258				clocks = <&cctl GD32_CLOCK_GPIOD>;
259				resets = <&rctl GD32_RESET_GPIOD>;
260				status = "disabled";
261			};
262
263			gpioe: gpio@48001000 {
264				compatible = "gd,gd32-gpio";
265				gpio-controller;
266				#gpio-cells = <2>;
267				reg = <0x48001000 0x400>;
268				clocks = <&cctl GD32_CLOCK_GPIOE>;
269				resets = <&rctl GD32_RESET_GPIOE>;
270				status = "disabled";
271			};
272
273			gpiof: gpio@48001400 {
274				compatible = "gd,gd32-gpio";
275				gpio-controller;
276				#gpio-cells = <2>;
277				reg = <0x48001400 0x400>;
278				clocks = <&cctl GD32_CLOCK_GPIOF>;
279				resets = <&rctl GD32_RESET_GPIOF>;
280				status = "disabled";
281			};
282		};
283
284		timer0: timer@40012c00 {
285			compatible = "gd,gd32-timer";
286			reg = <0x40012c00 0x400>;
287			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
288			interrupt-names = "brk", "up", "trgcom", "cc";
289			clocks = <&cctl GD32_CLOCK_TIMER0>;
290			resets = <&rctl GD32_RESET_TIMER0>;
291			is-advanced;
292			channels = <4>;
293			status = "disabled";
294
295			pwm {
296				compatible = "gd,gd32-pwm";
297				status = "disabled";
298				#pwm-cells = <3>;
299			};
300		};
301
302		timer1: timer@40000000 {
303			compatible = "gd,gd32-timer";
304			reg = <0x40000000 0x400>;
305			interrupts = <28 0>;
306			interrupt-names = "global";
307			clocks = <&cctl GD32_CLOCK_TIMER1>;
308			resets = <&rctl GD32_RESET_TIMER1>;
309			is-32bit;
310			channels = <4>;
311			status = "disabled";
312
313			pwm {
314				compatible = "gd,gd32-pwm";
315				status = "disabled";
316				#pwm-cells = <3>;
317			};
318		};
319
320		timer5: timer@40001000 {
321			compatible = "gd,gd32-timer";
322			reg = <0x40001000 0x400>;
323			interrupts = <54 0>;
324			interrupt-names = "global";
325			clocks = <&cctl GD32_CLOCK_TIMER5>;
326			resets = <&rctl GD32_RESET_TIMER5>;
327			channels = <0>;
328			status = "disabled";
329		};
330
331		timer6: timer@40001400 {
332			compatible = "gd,gd32-timer";
333			reg = <0x40001400 0x400>;
334			interrupts = <55 0>;
335			interrupt-names = "global";
336			clocks = <&cctl GD32_CLOCK_TIMER6>;
337			resets = <&rctl GD32_RESET_TIMER6>;
338			channels = <0>;
339			status = "disabled";
340		};
341
342		timer7: timer@40013400 {
343			compatible = "gd,gd32-timer";
344			reg = <0x40013400 0x400>;
345			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
346			interrupt-names = "brk", "up", "trgcom", "cc";
347			clocks = <&cctl GD32_CLOCK_TIMER7>;
348			resets = <&rctl GD32_RESET_TIMER7>;
349			is-advanced;
350			channels = <4>;
351			status = "disabled";
352
353			pwm {
354				compatible = "gd,gd32-pwm";
355				status = "disabled";
356				#pwm-cells = <3>;
357			};
358		};
359
360		timer19: timer@40015000 {
361			compatible = "gd,gd32-timer";
362			reg = <0x40015000 0x400>;
363			interrupts = <43 0>;
364			interrupt-names = "global";
365			clocks = <&cctl GD32_CLOCK_TIMER19>;
366			resets = <&rctl GD32_RESET_TIMER19>;
367			channels = <2>;
368			status = "disabled";
369
370			pwm {
371				compatible = "gd,gd32-pwm";
372				status = "disabled";
373				#pwm-cells = <3>;
374			};
375		};
376
377		timer20: timer@40015400 {
378			compatible = "gd,gd32-timer";
379			reg = <0x40015400 0x400>;
380			interrupts = <44 0>;
381			interrupt-names = "global";
382			clocks = <&cctl GD32_CLOCK_TIMER20>;
383			resets = <&rctl GD32_RESET_TIMER20>;
384			channels = <1>;
385			status = "disabled";
386
387			pwm {
388				compatible = "gd,gd32-pwm";
389				status = "disabled";
390				#pwm-cells = <3>;
391			};
392		};
393
394		dma0: dma@40020000 {
395			compatible = "gd,gd32-dma";
396			reg = <0x40020000 0x400>;
397			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
398				     <15 0>, <16 0>, <17 0>, <47 0>;
399			clocks = <&cctl GD32_CLOCK_DMA0>;
400			dma-channels = <7>;
401			gd,mem2mem;
402			#dma-cells = <2>;
403			status = "disabled";
404		};
405
406		dma1: dma@40020400 {
407			compatible = "gd,gd32-dma";
408			reg = <0x40020400 0x400>;
409			interrupts = <56 0>, <57 0>, <58 0>,
410				     <59 0>, <60 0>;
411			clocks = <&cctl GD32_CLOCK_DMA1>;
412			dma-channels = <5>;
413			gd,mem2mem;
414			#dma-cells = <2>;
415			status = "disabled";
416		};
417	};
418};
419
420&nvic {
421	arm,num-irq-priority-bits = <4>;
422};
423