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Searched refs:GD32_RESET_USART0 (Results 1 – 16 of 16) sorted by relevance

/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h34 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32vf103.h40 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32l23x.h68 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32a50x.h66 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32f403.h43 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32e10x.h41 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32e50x.h43 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U) macro
Dgd32f4xx.h93 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 4U) macro
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32l23x/
Dgd32l23x.dtsi74 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f3x0.dtsi70 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi98 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi80 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi85 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi71 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f403/
Dgd32f403.dtsi79 resets = <&rctl GD32_RESET_USART0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi77 resets = <&rctl GD32_RESET_USART0>;