Searched refs:GD32_RESET_TIMER6 (Results 1 – 13 of 13) sorted by relevance
48 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
44 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
47 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
53 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
52 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
58 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
68 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
402 resets = <&rctl GD32_RESET_TIMER6>;
337 resets = <&rctl GD32_RESET_TIMER6>;
343 resets = <&rctl GD32_RESET_TIMER6>;
368 resets = <&rctl GD32_RESET_TIMER6>;
496 resets = <&rctl GD32_RESET_TIMER6>;