Home
last modified time | relevance | path

Searched refs:GD32_RESET_TIMER6 (Results 1 – 13 of 13) sorted by relevance

/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/reset/
Dgd32vf103.h48 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32l23x.h44 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32a50x.h47 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32f403.h53 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32e10x.h52 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32e50x.h58 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
Dgd32f4xx.h68 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
/Zephyr-Core-3.4.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi402 resets = <&rctl GD32_RESET_TIMER6>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi337 resets = <&rctl GD32_RESET_TIMER6>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi402 resets = <&rctl GD32_RESET_TIMER6>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi343 resets = <&rctl GD32_RESET_TIMER6>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f403/
Dgd32f403.dtsi368 resets = <&rctl GD32_RESET_TIMER6>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi496 resets = <&rctl GD32_RESET_TIMER6>;