Searched refs:GD32_RESET_SPI1 (Results 1 – 12 of 12) sorted by relevance
45 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
50 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
49 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
58 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
57 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
63 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
73 #define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U) macro
199 resets = <&rctl GD32_RESET_SPI1>;
154 resets = <&rctl GD32_RESET_SPI1>;
135 resets = <&rctl GD32_RESET_SPI1>;
209 resets = <&rctl GD32_RESET_SPI1>;