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Searched refs:GD32_RESET_I2C0 (Results 1 – 12 of 12) sorted by relevance

/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/reset/
Dgd32vf103.h56 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32l23x.h54 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32a50x.h52 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32f403.h64 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32e10x.h63 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32e50x.h69 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
Dgd32f4xx.h79 #define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U) macro
/Zephyr-Core-3.4.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi179 resets = <&rctl GD32_RESET_I2C0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi121 resets = <&rctl GD32_RESET_I2C0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi154 resets = <&rctl GD32_RESET_I2C0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi130 resets = <&rctl GD32_RESET_I2C0>;
/Zephyr-Core-3.4.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi163 resets = <&rctl GD32_RESET_I2C0>;