| /Zephyr-Core-2.7.6/drivers/can/ |
| D | can_stm32.h | 32 #define CAN_BANK_IN_LIST_MODE(can, bank) ((can)->FM1R & (1U << (bank))) argument
33 #define CAN_BANK_IN_32BIT_MODE(can, bank) ((can)->FS1R & (1U << (bank))) argument
34 #define CAN_IN_16BIT_LIST_MODE(can, bank) (CAN_BANK_IN_LIST_MODE(can, bank) && \ argument
35 !CAN_BANK_IN_32BIT_MODE(can, bank))
36 #define CAN_IN_16BIT_MASK_MODE(can, bank) (!CAN_BANK_IN_LIST_MODE(can, bank) && \ argument
37 !CAN_BANK_IN_32BIT_MODE(can, bank))
38 #define CAN_IN_32BIT_LIST_MODE(can, bank) (CAN_BANK_IN_LIST_MODE(can, bank) && \ argument
39 CAN_BANK_IN_32BIT_MODE(can, bank))
40 #define CAN_IN_32BIT_MASK_MODE(can, bank) (!CAN_BANK_IN_LIST_MODE(can, bank) && \ argument
41 CAN_BANK_IN_32BIT_MODE(can, bank))
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| /Zephyr-Core-2.7.6/arch/arc/core/mpu/ |
| D | arc_mpu_v6_internal.h | 65 static inline void _bank_select(uint32_t bank) in _bank_select() argument
70 z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, val | bank); in _bank_select()
78 uint32_t bank = index / ARC_FEATURE_MPU_BANK_SIZE; in _region_init() local
107 _bank_select(bank); in _region_init()
150 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_enabled_region() local
153 _bank_select(bank); in _is_enabled_region()
166 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_in_region() local
169 _bank_select(bank); in _is_in_region()
188 uint32_t bank = r_index / ARC_FEATURE_MPU_BANK_SIZE; in _is_user_accessible_region() local
191 _bank_select(bank); in _is_user_accessible_region()
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| /Zephyr-Core-2.7.6/soc/arc/snps_arc_iot/ |
| D | sysconf.c | 168 void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio8b_dbclk_div() argument
170 if (bank == GPIO8B_BANK0) { in arc_iot_gpio8b_dbclk_div()
173 } else if (bank == GPIO8B_BANK1) { in arc_iot_gpio8b_dbclk_div()
176 } else if (bank == GPIO8B_BANK2) { in arc_iot_gpio8b_dbclk_div()
179 } else if (bank == GPIO8B_BANK3) { in arc_iot_gpio8b_dbclk_div()
185 void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div) in arc_iot_gpio4b_dbclk_div() argument
187 if (bank == GPIO4B_BANK0) { in arc_iot_gpio4b_dbclk_div()
190 } else if (bank == GPIO4B_BANK1) { in arc_iot_gpio4b_dbclk_div()
193 } else if (bank == GPIO4B_BANK2) { in arc_iot_gpio4b_dbclk_div()
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| D | sysconf.h | 148 extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div);
149 extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div);
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| /Zephyr-Core-2.7.6/drivers/flash/ |
| D | flash_ite_it8xxx2.c | 85 #define FWP_REG(bank) (bank / 8) argument
86 #define FWP_MASK(bank) (1 << (bank % 8)) argument
369 int bank; in flash_protect_banks() local
371 for (bank = start_bank; bank < start_bank + bank_count; bank++) { in flash_protect_banks()
373 IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank); in flash_protect_banks()
376 IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank); in flash_protect_banks()
379 IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank); in flash_protect_banks()
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| D | flash_stm32h7x.c | 51 int bank; member
200 sector.bank = 1; in get_sector()
205 sector.bank = 1; in get_sector()
209 sector.bank = 2; in get_sector()
214 sector.bank = 2; in get_sector()
219 sector.bank = 0; in get_sector()
226 sector.bank = 1; in get_sector()
231 sector.bank = 0; in get_sector()
246 if (sector.bank == 0) { in erase_sector()
297 if (sector.bank == 0) { in wait_write_queue()
[all …]
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| /Zephyr-Core-2.7.6/drivers/clock_control/ |
| D | clock_control_esp32.c | 259 uint32_t bank = GET_REG_BANK(sys); in clock_control_esp32_on() local
262 __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT); in clock_control_esp32_on()
264 esp32_set_mask32(BIT(offset), clock_control_regs[bank].clk); in clock_control_esp32_on()
265 esp32_clear_mask32(BIT(offset), clock_control_regs[bank].rst); in clock_control_esp32_on()
273 uint32_t bank = GET_REG_BANK(sys); in clock_control_esp32_off() local
276 __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT); in clock_control_esp32_off()
278 esp32_clear_mask32(BIT(offset), clock_control_regs[bank].clk); in clock_control_esp32_off()
279 esp32_set_mask32(BIT(offset), clock_control_regs[bank].rst); in clock_control_esp32_off()
287 uint32_t bank = GET_REG_BANK(sys); in clock_control_esp32_get_status() local
290 if (DPORT_GET_PERI_REG_MASK(clock_control_regs[bank].clk, BIT(offset))) { in clock_control_esp32_get_status()
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| /Zephyr-Core-2.7.6/boards/arm/nucleo_l053r8/support/ |
| D | openocd.cfg | 11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
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| /Zephyr-Core-2.7.6/boards/arm/nucleo_l073rz/support/ |
| D | openocd.cfg | 11 # Add the second flash bank.
13 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
|
| /Zephyr-Core-2.7.6/dts/arm64/qemu-virt/ |
| D | qemu-virt-a53.dtsi | 83 bank-width = <4>;
86 * second flash bank for now
|
| /Zephyr-Core-2.7.6/drivers/usb/device/ |
| D | usb_dc_sam0.c | 349 UsbDeviceDescBank *bank; in usb_dc_ep_configure() local
386 bank = &desc->DeviceDescBank[1]; in usb_dc_ep_configure()
388 bank = &desc->DeviceDescBank[0]; in usb_dc_ep_configure()
391 buf = (void *)bank->ADDR.reg; in usb_dc_ep_configure()
393 if (bank->PCKSIZE.bit.SIZE != size || buf == NULL) { in usb_dc_ep_configure()
401 bank->PCKSIZE.bit.SIZE = size; in usb_dc_ep_configure()
402 bank->ADDR.reg = (uintptr_t)buf; in usb_dc_ep_configure()
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| /Zephyr-Core-2.7.6/boards/riscv/rv32m1_vega/support/ |
| D | openocd_rv32m1_vega_zero_riscy.cfg | 46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
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| D | openocd_rv32m1_vega_ri5cy.cfg | 46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
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| /Zephyr-Core-2.7.6/boards/riscv/hifive_unleashed/support/ |
| D | openocd_hifive_unleashed.cfg | 22 flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
|
| /Zephyr-Core-2.7.6/boards/riscv/hifive_unmatched/support/ |
| D | openocd_hifive_unleashed.cfg | 22 flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000
|
| /Zephyr-Core-2.7.6/arch/arc/ |
| D | Kconfig | 144 bank. If fast interrupts are supported (FIRQ), the 2nd
145 register bank, in the set, will be used by FIRQ interrupts.
147 register bank, the fast interrupt handler must save
150 to use second register bank - otherwise all interrupts will use
151 same register bank. Such configuration isn't supported in software
162 other regs will be saved according to the number of register bank;
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| /Zephyr-Core-2.7.6/boards/sparc/generic_leon3/doc/ |
| D | index.rst | 103 Allocated 4096 KiB SRAM memory, in 1 bank at 0x40000000
104 Allocated 32 MiB SDRAM memory, in 1 bank at 0x60000000
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| /Zephyr-Core-2.7.6/boards/arm/stm32f429i_disc1/ |
| D | stm32f429i_disc1.dts | 140 bank@1 {
|
| /Zephyr-Core-2.7.6/soc/riscv/openisa_rv32m1/ |
| D | linker.ld | 67 * a vector table at the end of its flash bank. They are relocatable
71 * flash bank.)
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| /Zephyr-Core-2.7.6/boards/arm/stm32h747i_disco/ |
| D | stm32h747i_disco_m7.dts | 148 bank@1 {
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| /Zephyr-Core-2.7.6/dts/riscv/ |
| D | virt.dtsi | 22 bank-width = < 0x04 >;
|
| /Zephyr-Core-2.7.6/drivers/i2c/ |
| D | i2c_npcx_controller.c | 196 static inline void i2c_ctrl_bank_sel(const struct device *dev, int bank) in i2c_ctrl_bank_sel() argument
200 if (bank) { in i2c_ctrl_bank_sel()
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| /Zephyr-Core-2.7.6/soc/xtensa/esp32/ |
| D | linker.ld | 35 * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage)
38 * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage)
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| /Zephyr-Core-2.7.6/boards/arc/nsim/doc/ |
| D | index.rst | 20 … which includes normal ARC EM features and ARC MPUv2, specially with one register bank and fast irq
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| /Zephyr-Core-2.7.6/boards/arm/nucleo_l432kc/doc/ |
| D | index.rst | 64 - Up to 256 KB single bank Flash, proprietary code readout protection
|
