1# ARC options 2 3# Copyright (c) 2014, 2019 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "ARC Options" 7 depends on ARC 8 9config ARCH 10 default "arc" 11 12 13config CPU_ARCEM 14 bool 15 select ATOMIC_OPERATIONS_C 16 help 17 This option signifies the use of an ARC EM CPU 18 19config CPU_ARCHS 20 bool 21 select ATOMIC_OPERATIONS_BUILTIN 22 help 23 This option signifies the use of an ARC HS CPU 24 25 26choice 27 prompt "ARC Instruction Set" 28 default ISA_ARCV2 29 30config ISA_ARCV2 31 bool "ARC ISA v2" 32 select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2) 33 select ARCH_HAS_USERSPACE if ARC_MPU 34 select USE_SWITCH 35 select USE_SWITCH_SUPPORTED 36 help 37 v2 ISA for the ARC-HS & ARC-EM cores 38 39config ISA_ARCV3 40 bool "ARC ISA v3" 41 select USE_SWITCH 42 select USE_SWITCH_SUPPORTED 43 44endchoice 45 46if ISA_ARCV2 47 48config CPU_EM4 49 bool 50 select CPU_ARCEM 51 help 52 If y, the SoC uses an ARC EM4 CPU 53 54config CPU_EM4_DMIPS 55 bool 56 select CPU_ARCEM 57 help 58 If y, the SoC uses an ARC EM4 DMIPS CPU 59 60config CPU_EM4_FPUS 61 bool 62 select CPU_ARCEM 63 help 64 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision 65 floating-point extension 66 67config CPU_EM4_FPUDA 68 bool 69 select CPU_ARCEM 70 help 71 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision 72 floating-point and double assist instructions 73 74config CPU_EM6 75 bool 76 select CPU_ARCEM 77 help 78 If y, the SoC uses an ARC EM6 CPU 79 80config CPU_HS3X 81 bool 82 select CPU_ARCHS 83 help 84 If y, the SoC uses an ARC HS3x or HS4x CPU 85 86endif #ISA_ARCV2 87 88if ISA_ARCV3 89 90config CPU_HS6X 91 bool 92 select CPU_ARCHS 93 select 64BIT 94 help 95 If y, the SoC uses an ARC HS6x CPU 96 97endif #ISA_ARCV3 98 99config FP_FPU_DA 100 bool 101 102menu "ARC CPU Options" 103 104config ARC_HAS_ZOL 105 bool 106 depends on ISA_ARCV2 107 default y 108 help 109 ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops. 110 Architecturally ZOL provides 111 - LPcc instruction 112 - LP_COUNT core reg 113 - LP_START, LP_END aux regs 114 Disabling this option removes usage of ZOL regs from code 115 116config NUM_IRQ_PRIO_LEVELS 117 int "Number of supported interrupt priority levels" 118 range 1 16 119 help 120 Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. 121 The minimum value is 1. 122 123 The BSP must provide a valid default for proper operation. 124 125config NUM_IRQS 126 int "Upper limit of interrupt numbers/IDs used" 127 range 17 256 128 help 129 Interrupts available will be 0 to NUM_IRQS-1. 130 The minimum value is 17 as the first 16 entries in the vector 131 table are for CPU exceptions. 132 133 The BSP must provide a valid default. This drives the size of the 134 vector table. 135 136config RGF_NUM_BANKS 137 int "Number of General Purpose Register Banks" 138 depends on ARC_FIRQ 139 depends on NUM_IRQ_PRIO_LEVELS > 1 140 range 1 2 141 default 2 142 help 143 The ARC CPU can be configured to have more than one register 144 bank. If fast interrupts are supported (FIRQ), the 2nd 145 register bank, in the set, will be used by FIRQ interrupts. 146 If fast interrupts are supported but there is only 1 147 register bank, the fast interrupt handler must save 148 and restore general purpose registers. 149 NOTE: it's required to have more than one interrupt priority level 150 to use second register bank - otherwise all interrupts will use 151 same register bank. Such configuration isn't supported in software 152 and it is not beneficial from the performance point of view. 153 154config ARC_FIRQ 155 bool "FIRQ enable" 156 depends on ISA_ARCV2 157 depends on NUM_IRQ_PRIO_LEVELS > 1 158 default y 159 help 160 Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts 161 with highest priority, status32 and pc will be saved in aux regs, 162 other regs will be saved according to the number of register bank; 163 If FIRQ is disabled, the handle of interrupts with highest priority 164 will be same with other interrupts. 165 NOTE: we don't allow the configuration with FIRQ enabled and only one 166 interrupt priority level (so all interrupts are FIRQ). Such 167 configuration isn't supported in software and it is not beneficial 168 from the performance point of view. 169 170config ARC_FIRQ_STACK 171 bool "Enable separate firq stack" 172 depends on ARC_FIRQ && RGF_NUM_BANKS > 1 173 help 174 Use separate stack for FIRQ handing. When the fast irq is also a direct 175 irq, this will get the minimal interrupt latency. 176 177config ARC_FIRQ_STACK_SIZE 178 int "FIRQ stack size" 179 depends on ARC_FIRQ_STACK 180 default 1024 181 help 182 The size of firq stack. 183 184config ARC_HAS_STACK_CHECKING 185 bool "ARC has STACK_CHECKING" 186 depends on ISA_ARCV2 187 default y 188 help 189 ARC is configured with STACK_CHECKING which is a mechanism for 190 checking stack accesses and raising an exception when a stack 191 overflow or underflow is detected. 192 193config ARC_CONNECT 194 bool "ARC has ARC connect" 195 select SCHED_IPI_SUPPORTED 196 help 197 ARC is configured with ARC CONNECT which is a hardware for connecting 198 multi cores. 199 200config ARC_STACK_CHECKING 201 bool 202 select NO_UNUSED_STACK_INSPECTION 203 help 204 Use ARC STACK_CHECKING to do stack protection 205 206config ARC_STACK_PROTECTION 207 bool 208 default y if HW_STACK_PROTECTION 209 select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING 210 select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU && ARC_MPU_VER !=2) 211 select THREAD_STACK_INFO 212 help 213 This option enables either: 214 - The ARC stack checking, or 215 - the MPU-based stack guard 216 to cause a system fatal error 217 if the bounds of the current process stack are overflowed. 218 The two stack guard options are mutually exclusive. The 219 selection of the ARC stack checking is 220 prioritized over the MPU-based stack guard. 221 222config ARC_USE_UNALIGNED_MEM_ACCESS 223 bool "Enable unaligned access in HW" 224 default y if CPU_ARCHS 225 depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS 226 help 227 ARC EM cores w/o secure shield 2+2 mode support might be configured 228 to support unaligned memory access which is then disabled by default. 229 Enable unaligned access in hardware and make software to use it. 230 231config FAULT_DUMP 232 int "Fault dump level" 233 default 2 234 range 0 2 235 help 236 Different levels for display information when a fault occurs. 237 238 2: The default. Display specific and verbose information. Consumes 239 the most memory (long strings). 240 241 1: Display general and short information. Consumes less memory 242 (short strings). 243 244 0: Off. 245 246config GEN_ISR_TABLES 247 default y 248 249config GEN_IRQ_START_VECTOR 250 default 16 251 252config HARVARD 253 bool "Harvard Architecture" 254 help 255 The ARC CPU can be configured to have two busses; 256 one for instruction fetching and another that serves as a data bus. 257 258config CODE_DENSITY 259 bool "Code Density Option" 260 help 261 Enable code density option to get better code density 262 263config ARC_HAS_ACCL_REGS 264 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" 265 default y if CPU_HS3X 266 default y if FPU 267 help 268 Depending on the configuration, CPU can contain accumulator reg-pair 269 (also referred to as r58:r59). These can also be used by gcc as GPR so 270 kernel needs to save/restore per process 271 272config ARC_HAS_SECURE 273 bool "ARC has SecureShield" 274 depends on ISA_ARCV2 275 select CPU_HAS_TEE 276 select ARCH_HAS_TRUSTED_EXECUTION 277 help 278 This option is enabled when ARC core supports secure mode 279 280config SJLI_TABLE_SIZE 281 int "SJLI table size" 282 depends on ARC_SECURE_FIRMWARE 283 default 8 284 help 285 The size of sjli (Secure Jump and Link Indexed) table. The 286 code in normal mode call secure services in secure mode through 287 sjli instruction. 288 289config ARC_SECURE_FIRMWARE 290 bool "Generate Secure Firmware" 291 depends on ARC_HAS_SECURE 292 default y if TRUSTED_EXECUTION_SECURE 293 help 294 This option indicates that we are building a Zephyr image that 295 is intended to execute in secure mode. The option is only 296 applicable to ARC processors that implement the SecureShield. 297 298 This option enables Zephyr to include code that executes in 299 secure mode, as well as to exclude code that is designed to 300 execute only in normal mode. 301 302 Code executing in secure mode has access to both the secure 303 and normal resources of the ARC processors. 304 305config ARC_NORMAL_FIRMWARE 306 bool "Generate Normal Firmware" 307 depends on !ARC_SECURE_FIRMWARE 308 depends on ARC_HAS_SECURE 309 default y if TRUSTED_EXECUTION_NONSECURE 310 help 311 This option indicates that we are building a Zephyr image that 312 is intended to execute in normal mode. Execution of this 313 image is triggered by secure firmware that executes in secure 314 mode. The option is only applicable to ARC processors that 315 implement the SecureShield. 316 317 This option enables Zephyr to include code that executes in 318 normal mode only, as well as to exclude code that is 319 designed to execute only in secure mode. 320 321 Code executing in normal mode has no access to secure 322 resources of the ARC processors, and, therefore, it shall avoid 323 accessing them. 324 325menu "ARC MPU Options" 326depends on CPU_HAS_MPU 327 328config ARC_MPU_ENABLE 329 bool "Enable MPU" 330 select ARC_MPU 331 help 332 Enable MPU 333 334source "arch/arc/core/mpu/Kconfig" 335 336endmenu 337 338config DCACHE_LINE_SIZE 339 default 32 340 341config ARC_EXCEPTION_STACK_SIZE 342 int "ARC exception handling stack size" 343 default 768 if !64BIT 344 default 2048 if 64BIT 345 help 346 Size in bytes of exception handling stack which is at the top of 347 interrupt stack to get smaller memory footprint because exception 348 is not frequent. To reduce the impact on interrupt handling, 349 especially nested interrupt, it cannot be too large. 350 351endmenu 352 353config ARC_EXCEPTION_DEBUG 354 bool "Unhandled exception debugging information" 355 default n 356 depends on PRINTK || LOG 357 help 358 Print human-readable information about exception vectors, cause codes, 359 and parameters, at a cost of code/data size for the human-readable 360 strings. 361 362endmenu 363 364config MAIN_STACK_SIZE 365 default 4096 if 64BIT 366 367config ISR_STACK_SIZE 368 default 4096 if 64BIT 369 370config SYSTEM_WORKQUEUE_STACK_SIZE 371 default 4096 if 64BIT 372 373config IDLE_STACK_SIZE 374 default 1024 if 64BIT 375 376config IPM_CONSOLE_STACK_SIZE 377 default 2048 if 64BIT 378 379config TEST_EXTRA_STACKSIZE 380 default 2048 if 64BIT 381 382config CMSIS_THREAD_MAX_STACK_SIZE 383 default 2048 if 64BIT 384 385config CMSIS_V2_THREAD_MAX_STACK_SIZE 386 default 2048 if 64BIT 387 388config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 389 default 2048 if 64BIT 390
