Searched +full:xtal +full:- +full:single +full:- +full:ended (Results 1 – 7 of 7) sorted by relevance
2 # SPDX-License-Identifier: Apache-2.06 compatible: "microchip,xec-pcr"8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]14 core-clock-div:17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock19 slow-clock-div:25 pll-32k-src:30 periph-32k-src:35 xtal-single-ended:37 description: Use single ended crystal connection to XTAL2 pin.[all …]
4 * SPDX-License-Identifier: Apache-2.07 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;15 xtal-single-ended;16 internal-osc-disable;19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */25 /* pinctrl-0 = <&clk_32khz_in_gpio16529 pinctrl-names = "default";
4 * SPDX-License-Identifier: Apache-2.016 /* Offset 0x00 Power-Fail and Reset Status */48 /* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */50 /* disable XTAL high startup current */77 * Monotonic Counter least significant word (32-bit), read-only.82 /* Monotonic Counter most significant word (32-bit). Read-Write */
4 * SPDX-License-Identifier: Apache-2.011 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()30 r = pcr->OSC_ID; in pcr_clock_regs()33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()36 r = pcr->SLOW_CLK_CTRL; in pcr_clock_regs()43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()48 LOG_INF("32KHz clock source is XTAL"); in vbat_clock_regs()50 LOG_INF("XTAL configured for single-ended using XTAL2 pin" in vbat_clock_regs()[all …]
4 * SPDX-License-Identifier: Apache-2.015 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>30 * 32KHz period counter minimum for pass/fail: 16-bit31 * 32KHz period counter maximum for pass/fail: 16-bit32 * 32KHz duty cycle variation max for pass/fail: 16-bit33 * 32KHz valid count minimum: 8-bit99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];157 #define XEC_CC_VBATR_CS_XTAL_DHC BIT(10) /* disable high XTAL startup current */158 #define XEC_CC_VBATR_CS_XTAL_CNTR_MSK 0x1800u /* XTAL amplifier gain control */169 #define XEC_CC_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u /* VTR 32KHZ_IN, VBAT XTAL */[all …]
