| /Zephyr-latest/drivers/sensor/ti/fdc2x1x/ |
| D | fdc2x1x.h | 61 #define FDC2X1X_REG_READ(x) (((x & 0xFF) << 1) | FDC2X1X_READ) argument
62 #define FDC2X1X_REG_WRITE(x) ((x & 0xFF) << 1) argument
63 #define FDC2X1X_TO_I2C_REG(x) ((x) >> 1) argument
67 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_SET(x) (((x) & 0x3) << 12) argument
68 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_GET(x) (((x) >> 12) & 0x3) argument
70 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_SET(x) ((x) & 0x1FF) argument
71 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_GET(x) (((x) >> 0) & 0x1FF) argument
74 #define FDC2X1X_STATUS_ERR_CHAN(x) (((x) >> 14) & 0x3) argument
75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1) argument
76 #define FDC2X1X_STATUS_ERR_AHW(x) (((x) >> 10) & 0x1) argument
[all …]
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| /Zephyr-latest/drivers/flash/ |
| D | flash_cadence_qspi_nor_ll.h | 24 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x) argument
33 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
41 #define CAD_QSPI_DELAY_CSSOT(x) (FIELD_GET(0xff, (x)) << 0) argument
42 #define CAD_QSPI_DELAY_CSEOT(x) (FIELD_GET(0xff, (x)) << 8) argument
43 #define CAD_QSPI_DELAY_CSDADS(x) (FIELD_GET(0xff, (x)) << 16) argument
44 #define CAD_QSPI_DELAY_CSDA(x) (FIELD_GET(0xff, (x)) << 24) argument
47 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) argument
48 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) argument
49 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x) ((x) << 16) argument
[all …]
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| D | flash_cadence_nand_ll.h | 18 #define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x)) argument
19 #define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x)) argument
20 #define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x)) argument
21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x)) argument
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x)) argument
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x)) argument
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x)) argument
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x)) argument
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x)) argument
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x)) argument
[all …]
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| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | prci.h | 25 #define ROSC_DIV(x) (((x) & 0x2F) << 0) argument
26 #define ROSC_TRIM(x) (((x) & 0x1F) << 16) argument
27 #define ROSC_EN(x) (((x) & 0x1) << 30) argument
28 #define ROSC_RDY(x) (((x) & 0x1) << 31) argument
30 #define XOSC_EN(x) (((x) & 0x1) << 30) argument
31 #define XOSC_RDY(x) (((x) & 0x1) << 31) argument
33 #define PLL_R(x) (((x) & 0x7) << 0) argument
35 #define PLL_F(x) (((x) & 0x3F) << 4) argument
36 #define PLL_Q(x) (((x) & 0x3) << 10) argument
37 #define PLL_SEL(x) (((x) & 0x1) << 16) argument
[all …]
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| /Zephyr-latest/drivers/sensor/ti/tmp108/ |
| D | tmp108.h | 47 #define TI_TMP108_MODE_SHUTDOWN(x) 0 argument
48 #define TI_TMP108_MODE_ONE_SHOT(x) (TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_SLEEP(x)) argument
49 #define TI_TMP108_MODE_CONTINUOUS(x) TI_TMP108_CONF_M1(x) argument
50 #define TI_TMP108_MODE_MASK(x) ~(TI_TMP108_CONF_M0(x) | \ argument
51 TI_TMP108_CONF_M1(x) | \
52 TI_TMP108_CONF_SLEEP(x))
54 #define TI_TMP108_FREQ_4_SECS(x) 0 argument
55 #define TI_TMP108_FREQ_1_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR0) argument
56 #define TI_TMP108_FREQ_4_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR1) argument
57 #define TI_TMP108_FREQ_16_HZ(x) (TI_TMP108_GET_CONF(x, CONF_CR1) | \ argument
[all …]
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| /Zephyr-latest/include/zephyr/toolchain/ |
| D | xcc.h | 52 #define __INT8_C(x) x argument
56 #define INT8_C(x) __INT8_C(x) argument
60 #define __UINT8_C(x) x ## U argument
64 #define UINT8_C(x) __UINT8_C(x) argument
68 #define __INT16_C(x) x argument
72 #define INT16_C(x) __INT16_C(x) argument
76 #define __UINT16_C(x) x ## U argument
80 #define UINT16_C(x) __UINT16_C(x) argument
84 #define __INT32_C(x) x argument
88 #define INT32_C(x) __INT32_C(x) argument
[all …]
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| D | llvm.h | 65 #define __INT64_C(x) int_c(x, __int_least64_c_suffix__) argument
66 #define __UINT64_C(x) uint_c(x, __int_least64_c_suffix__) argument
68 #define __INT64_C(x) x argument
69 #define __UINT64_C(x) x ## U argument
86 #define __INT32_C(x) int_c(x, __int_least32_c_suffix__) argument
87 #define __UINT32_C(x) uint_c(x, __int_least32_c_suffix__) argument
89 #define __INT32_C(x) x argument
90 #define __UINT32_C(x) x ## U argument
107 #define __INT16_C(x) int_c(x, __int_least16_c_suffix__) argument
108 #define __UINT16_C(x) uint_c(x, __int_least16_c_suffix__) argument
[all …]
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp_regs_v1.h | 30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
46 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
100 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
101 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
103 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
[all …]
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| D | ssp_regs_v2.h | 31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
101 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
102 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
104 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
[all …]
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| D | ssp_regs_v3.h | 32 #define PCMSyCM_OFFSET(x) 0x16 + 0x4*(x) argument
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
96 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
97 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
98 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
99 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x) argument
[all …]
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| /Zephyr-latest/modules/hal_nordic/nrfs/dvfs/ |
| D | ld_dvfs.c | 45 LOG_DBG("REGW: NRF_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
49 LOG_DBG("REGW: NRF_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
53 LOG_DBG("REGW: NRF_ABB->TRIM.PVTMONCYCLES[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
59 LOG_DBG("REGW: NRF_APPLICATION_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
63 LOG_DBG("REGW: NRF_APPLICATION_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
67 LOG_DBG("REGW: NRF_APPLICATION_ABB->TRIM.PVTMONCYCLES[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
89 LOG_DBG("REGW: NRF_ABB->CONFIG.CTRL1.MODE 0x%x, V: 0x%x", in ld_dvfs_clear_zbb()
166 LOG_DBG("REGW: NRF_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_configure_abb_for_transition()
170 LOG_DBG("REGW: NRF_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_configure_abb_for_transition()
174 LOG_DBG("REGW: NRF_ABB->TRIM.PVTMONCYCLES[%d] 0x%x, V: 0x%x", in ld_dvfs_configure_abb_for_transition()
[all …]
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| /Zephyr-latest/lib/libc/minimal/include/ |
| D | stdint.h | 127 #define __INT8_C(x) x argument
131 #define INT8_C(x) __INT8_C(x) argument
135 #define __UINT8_C(x) x ## U argument
139 #define UINT8_C(x) __UINT8_C(x) argument
143 #define __INT16_C(x) x argument
147 #define INT16_C(x) __INT16_C(x) argument
151 #define __UINT16_C(x) x ## U argument
155 #define UINT16_C(x) __UINT16_C(x) argument
159 #define __INT32_C(x) x argument
163 #define INT32_C(x) __INT32_C(x) argument
[all …]
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| /Zephyr-latest/scripts/coccinelle/ |
| D | noderef.cocci | 17 expression *x;
24 x = <+... sizeof(
25 - x
26 + *x
29 f(...,(T)(x),...,sizeof(
30 - x
31 + *x
35 - x
36 + *x
37 ),...,(T)(x),...)
[all …]
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| /Zephyr-latest/arch/nios2/core/ |
| D | fatal.c | 26 LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4); in z_nios2_fatal_error()
27 LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x", in z_nios2_fatal_error()
29 LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x", in z_nios2_fatal_error()
31 LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x", in z_nios2_fatal_error()
33 LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x", in z_nios2_fatal_error()
35 LOG_ERR("estatus: %08x", esf->estatus); in z_nios2_fatal_error()
122 LOG_ERR("Exception cause: %d ECCFTL: 0x%x", cause, eccftl); in z_nios2_fault()
128 LOG_ERR("Badaddr: 0x%x", badaddr_reg); in z_nios2_fault()
|
| /Zephyr-latest/drivers/sensor/adi/adxl372/ |
| D | adxl372.h | 42 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */
43 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */
48 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */
49 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */
54 #define ADXL372_OFFSET_X 0x20u /* X axis offset */
57 #define ADXL372_X_THRESH_ACT_H 0x23u /* X axis Activity Threshold [15:8] */
58 #define ADXL372_X_THRESH_ACT_L 0x24u /* X axis Activity Threshold [7:0] */
64 #define ADXL372_X_THRESH_INACT_H 0x2Au /* X axis Inactivity Threshold */
65 #define ADXL372_X_THRESH_INACT_L 0x2Bu /* X axis Inactivity Threshold */
72 #define ADXL372_X_THRESH_ACT2_H 0x32u /* X axis Activity2 Threshold [15:8] */
[all …]
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| /Zephyr-latest/samples/subsys/zbus/msg_subscriber/ |
| D | sample.yaml | 34 - "^.*?I: From listener foo_lis -> Acc x=1, y=10, z=100"
35 - "^.*?I: From msg subscriber bar_msg_sub1 -> Acc x=1, y=10, z=100"
36 - "^.*?I: From msg subscriber bar_msg_sub2 -> Acc x=1, y=10, z=100"
37 - "^.*?I: From msg subscriber bar_msg_sub3 -> Acc x=1, y=10, z=100"
38 - "^.*?I: From msg subscriber bar_msg_sub4 -> Acc x=1, y=10, z=100"
39 - "^.*?I: From msg subscriber bar_msg_sub5 -> Acc x=1, y=10, z=100"
40 - "^.*?I: From msg subscriber bar_msg_sub6 -> Acc x=1, y=10, z=100"
41 - "^.*?I: From msg subscriber bar_msg_sub7 -> Acc x=1, y=10, z=100"
42 - "^.*?I: From msg subscriber bar_msg_sub8 -> Acc x=1, y=10, z=100"
43 - "^.*?I: From msg subscriber bar_msg_sub9 -> Acc x=1, y=10, z=100"
[all …]
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| D | README.rst | 31 [0/1] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: qemu32,+nx,+pae
35 I: From listener foo_lis -> Acc x=1, y=10, z=100
36 I: From msg subscriber bar_msg_sub1 -> Acc x=1, y=10, z=100
37 I: From msg subscriber bar_msg_sub2 -> Acc x=1, y=10, z=100
38 I: From msg subscriber bar_msg_sub3 -> Acc x=1, y=10, z=100
39 I: From msg subscriber bar_msg_sub4 -> Acc x=1, y=10, z=100
40 I: From msg subscriber bar_msg_sub5 -> Acc x=1, y=10, z=100
41 I: From msg subscriber bar_msg_sub6 -> Acc x=1, y=10, z=100
42 I: From msg subscriber bar_msg_sub7 -> Acc x=1, y=10, z=100
43 I: From msg subscriber bar_msg_sub8 -> Acc x=1, y=10, z=100
[all …]
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| /Zephyr-latest/arch/arm/core/ |
| D | fatal.c | 23 LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x", in esf_dump()
25 LOG_ERR("r3/a4: 0x%08x r12/ip: 0x%08x r14/lr: 0x%08x", in esf_dump()
27 LOG_ERR(" xpsr: 0x%08x", esf->basic.xpsr); in esf_dump()
30 LOG_ERR("s[%2d]: 0x%08x s[%2d]: 0x%08x" in esf_dump()
31 " s[%2d]: 0x%08x s[%2d]: 0x%08x", in esf_dump()
39 LOG_ERR("d[%2d]: 0x%16llx d[%2d]: 0x%16llx" in esf_dump()
40 " d[%2d]: 0x%16llx d[%2d]: 0x%16llx", in esf_dump()
47 LOG_ERR("fpscr: 0x%08x", esf->fpu.fpscr); in esf_dump()
53 LOG_ERR("r4/v1: 0x%08x r5/v2: 0x%08x r6/v3: 0x%08x", in esf_dump()
55 LOG_ERR("r7/v4: 0x%08x r8/v5: 0x%08x r9/v6: 0x%08x", in esf_dump()
[all …]
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| /Zephyr-latest/samples/philosophers/src/ |
| D | phil_obj_abstract.h | 53 #define fork_init(x) k_sem_init(x, 1, 1) argument
55 #define take(x) k_sem_take(x, K_FOREVER) argument
56 #define drop(x) k_sem_give(x) argument
69 #define fork_init(x) k_mutex_init(x) argument
71 #define take(x) k_mutex_lock(x, K_FOREVER) argument
72 #define drop(x) k_mutex_unlock(x) argument
83 #define fork_init(x) do { \ argument
84 k_stack_init(x, (stack_data_t *)((x) + 1), 1); \
85 k_stack_push(x, MAGIC); \
88 #define take(x) do { \ argument
[all …]
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/ |
| D | test_stm32_clock_configuration.c | 67 "Expected SPI src: PLL1 Q (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected SPI src: PLL2 P (0x%x). Actual: 0x%x", in ZTEST()
75 "Expected SPI src: PLL3 P (0x%x). Actual: 0x%x", in ZTEST()
79 "Expected SPI src: PERCLK (0x%x). Actual: 0x%x", in ZTEST()
92 "Expected PERCK src: HSI_KER (0x%x). Actual: 0x%x", in ZTEST()
96 "Expected PERCK src: CSI_KER (0x%x). Actual: 0x%x", in ZTEST()
100 "Expected PERCK src: HSE (0x%x). Actual: 0x%x", in ZTEST()
103 zassert_true(0, "Unexpected PERCK domain_clk src (0x%x)", in ZTEST()
108 zassert_true(0, "Unexpected domain_clk src(0x%x)", pclken[1].bus); in ZTEST()
119 "Expected SPI clk: 0x%x. Actual SPI clk: 0x%x", in ZTEST()
|
| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | prci.h | 27 #define PLL_R(x) (((x) & 0x3f) << 0) argument
28 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
29 #define PLL_Q(x) (((x) & 0x7) << 15) argument
30 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
31 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
32 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
33 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
40 #define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0) argument
|
| /Zephyr-latest/arch/arc/core/ |
| D | fatal.c | 28 ARC_EXCEPTION_DUMP(" r0: 0x%" PRIxPTR " r1: 0x%" PRIxPTR " r2: 0x%" PRIxPTR in dump_arc_esf()
29 " r3: 0x%" PRIxPTR "", esf->r0, esf->r1, esf->r2, esf->r3); in dump_arc_esf()
30 ARC_EXCEPTION_DUMP(" r4: 0x%" PRIxPTR " r5: 0x%" PRIxPTR " r6: 0x%" PRIxPTR in dump_arc_esf()
31 " r7: 0x%" PRIxPTR "", esf->r4, esf->r5, esf->r6, esf->r7); in dump_arc_esf()
32 ARC_EXCEPTION_DUMP(" r8: 0x%" PRIxPTR " r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR in dump_arc_esf()
33 " r11: 0x%" PRIxPTR "", esf->r8, esf->r9, esf->r10, esf->r11); in dump_arc_esf()
34 ARC_EXCEPTION_DUMP("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR " pc: 0x%" PRIxPTR "", in dump_arc_esf()
36 ARC_EXCEPTION_DUMP(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", in dump_arc_esf()
39 ARC_EXCEPTION_DUMP("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR in dump_arc_esf()
40 " lp_count: 0x%" PRIxPTR "", esf->lp_end, esf->lp_start, esf->lp_count); in dump_arc_esf()
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | prci.h | 33 #define PLL_R(x) (((x) & 0x3f) << 0) argument
34 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
35 #define PLL_Q(x) (((x) & 0x7) << 15) argument
36 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
37 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
38 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
39 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
53 #define OUTDIV_PLLCKE(x) (((x) & 0x1) << 31) argument
58 #define CLKSEL_SEL(x) (((x) & 0x1) << 0) argument
71 #define COREPLLSEL_SEL(x) (((x) & 0x1) << 0) argument
|
| /Zephyr-latest/tests/kernel/common/src/ |
| D | printk.c | 75 "0x1 0x 1 0x 1 0x 1\n"
102 "0x1 0x 1 0x 1 0x 1\n"
118 "0x1 0x 1 0x 1 0x 1\n"
131 "0x1 0x 1 0x 1 0x 1\n"
144 "0x1 0x 1 0x 1 0x 1\n"
209 printk("0x%x 0x%02x 0x%04x 0x%08x 0x%016x\n", 1, 1, 1, 1, 1); in ZTEST()
210 printk("0x%x 0x%2x 0x%4x 0x%8x\n", 1, 1, 1, 1); in ZTEST()
215 printk("%-8u%-6d%-4x %8d\n", 0xFF, 42, 0xABCDEF, 42); in ZTEST()
217 printk("0x%x %p %-2p\n", hex, ptr, (char *)42); in ZTEST()
233 "0x%x 0x%02x 0x%04x 0x%08x 0x%016x\n", 1, 1, 1, 1, 1); in ZTEST()
[all …]
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| /Zephyr-latest/drivers/sensor/adi/adxl345/ |
| D | adxl345.h | 36 #define ADXL345_REG_READ(x) ((x & 0xFF) | ADXL345_READ_CMD) argument
62 #define ADXL345_COMPLEMENT_MASK(x) GENMASK(15, (x)) argument
72 #define ADXL345_STATUS_DOUBLE_TAP(x) (((x) >> 5) & 0x1) argument
73 #define ADXL345_STATUS_SINGLE_TAP(x) (((x) >> 6) & 0x1) argument
74 #define ADXL345_STATUS_DATA_RDY(x) (((x) >> 7) & 0x1) argument
78 #define ADXL345_INT_MAP_OVERRUN_MODE(x) (((x) & 0x1) << 0) argument
80 #define ADXL345_INT_MAP_WATERMARK_MODE(x) (((x) & 0x1) << 1) argument
82 #define ADXL345_INT_MAP_FREE_FALL_MODE(x) (((x) & 0x1) << 2) argument
84 #define ADXL345_INT_MAP_INACT_MODE(x) (((x) & 0x1) << 3) argument
86 #define ADXL345_INT_MAP_ACT_MODE(x) (((x) & 0x1) << 4) argument
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