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Searched +full:write +full:- +full:active +full:- +full:cycles (Results 1 – 21 of 21) sorted by relevance

/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,lcdic.yaml2 # SPDX-License-Identifier: Apache-2.0
5 NXP LCDIC Controller. This controller implements 8080 and SPI mode MIPI-DBI
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
21 nxp,swap-bytes:
27 reset-gpios:
28 type: phandle-array
34 nxp,write-inactive-cycles:
38 Set minimum count of write inactive cycles, as a multiple of the module
42 nxp,write-active-cycles:
46 Set minimum count of write active cycles, as a multiple of the module
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/Zephyr-latest/boards/shields/lcd_par_s035/boards/
Drd_rw612_bga.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
11 * - Depopulate resistors R78, R604, R598, R15, R245, R243, R11, R20, R237,
13 * - Populate resistors R286, R19, R246, R242, R123, R239, R124, R125, R236,
15 * - Remove jumper JP30
16 * - Set jumper JP40 to postion 1-2, JP38 to 1-2, and JP16 to position 2-3
21 * ON-ON-OFF (8 bit 8080 mode), and connect the following pins
23 * |-----------|-------------|----------|
62 slew-rate = "ultra";
67 mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT";
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/Zephyr-latest/dts/bindings/memory-controllers/
Dst,stm32-fmc-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
28 refresh-rate = <603>;
33 st,sdram-control = <STM32_FMC_SDRAM_NC_9
41 st,sdram-timing = <2 6 4 6 2 2 2>;
51 Note that you will find definitions for the st,sdram-control field at
52 dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
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Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
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/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
30 - "MSPI_IO_MODE_QUAD_1_1_4"
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/Zephyr-latest/drivers/watchdog/
Dwdt_dw.h1 /* SPDX-License-Identifier: Apache-2.0 */
19 * and programmed based on user-defined options.
66 #define RPL_PCLK_CYCLES2 0x0 /* 2 pclk cycles */
67 #define RPL_PCLK_CYCLES4 0x1 /* 4 pclk cycles */
68 #define RPL_PCLK_CYCLES8 0x2 /* 8 pclk cycles */
69 #define RPL_PCLK_CYCLES16 0x3 /* 16 pclk cycles */
70 #define RPL_PCLK_CYCLES32 0x4 /* 32 pclk cycles */
71 #define RPL_PCLK_CYCLES64 0x5 /* 64 pclk cycles */
72 #define RPL_PCLK_CYCLES128 0x6 /* 128 pclk cycles */
73 #define RPL_PCLK_CYCLES256 0x7 /* 256 pclk cycles */
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/Zephyr-latest/drivers/ps2/
Dps2_npcx_controller.c4 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/dt-bindings/clock/npcx_clock.h>
30 * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
39 * The max duration of a PS/2 clock is about 100 micro-seconds.
40 * A PS/2 transaction needs 11 clock cycles. It will take about 1.1 ms for a
56 * (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
71 ((struct ps2_reg *)((const struct ps2_npcx_ctrl_config *)(dev)->config)->base)
81 struct ps2_npcx_ctrl_data *const data = dev->data; in ps2_npcx_ctrl_configure()
85 return -EINVAL; in ps2_npcx_ctrl_configure()
89 return -EINVAL; in ps2_npcx_ctrl_configure()
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/Zephyr-latest/drivers/sdhc/
Dsdhc_spi.c4 * SPDX-License-Identifier: Apache-2.0
147 * to the card (this should result in 80 SCK cycles) in sdhc_spi_init_card()
149 const struct sdhc_spi_config *config = dev->config; in sdhc_spi_init_card()
150 struct sdhc_spi_data *data = dev->data; in sdhc_spi_init_card()
151 struct spi_config *spi_cfg = data->spi_cfg; in sdhc_spi_init_card()
154 if (spi_cfg->frequency == 0) { in sdhc_spi_init_card()
156 spi_cfg->frequency = SDMMC_CLOCK_400KHZ; in sdhc_spi_init_card()
159 /* Request SPI bus to be active */ in sdhc_spi_init_card()
160 if (pm_device_runtime_get(config->spi_dev) < 0) { in sdhc_spi_init_card()
161 return -EIO; in sdhc_spi_init_card()
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/Zephyr-latest/drivers/mspi/
Dmspi_dw.c4 * SPDX-License-Identifier: Apache-2.0
38 uint32_t write; member
122 struct mspi_dw_data *dev_data = dev->data; in tx_data()
123 const struct mspi_dw_config *dev_config = dev->config; in tx_data()
124 const uint8_t *buf_pos = dev_data->buf_pos; in tx_data()
125 const uint8_t *buf_end = dev_data->buf_end; in tx_data()
135 uint8_t bytes_per_frame_exp = dev_data->bytes_per_frame_exp; in tx_data()
136 uint8_t tx_fifo_depth = dev_config->tx_fifo_depth_minus_1 + 1; in tx_data()
157 if (--room == 0) { in tx_data()
159 - FIELD_GET(TXFLR_TXTFL_MASK, read_txflr(dev)); in tx_data()
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/Zephyr-latest/drivers/rtc/
Drtc_ll_stm32.c6 * SPDX-License-Identifier: Apache-2.0
56 * 2^20 clock cycles so it is suitable for the CALR register fields
62 /* Convert CALR register value (number of clock pulses added or removed each 2^20 clock cycles)
70 * added every 2^20 clock cycles
76 #define MIN_PPB -NB_PULSES_TO_PPB(MAX_CALM)
102 * After system reset, the RTC registers are protected against parasitic write access by the
104 * Hence, DBP bit must be set in order to enable RTC registers write access.
126 /* user-defined alarm mask, values from RTC_ALARM_TIME_MASK */
144 const struct rtc_stm32_config *cfg = dev->config; in rtc_stm32_configure()
158 (sync_prescaler != cfg->sync_prescaler) || in rtc_stm32_configure()
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/Zephyr-latest/drivers/spi/
Dspi_xlnx_axi_quadspi.c4 * SPDX-License-Identifier: Apache-2.0
105 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
107 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
116 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
121 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
122 struct xlnx_quadspi_data *data = dev->data; in xlnx_quadspi_cs_control()
123 struct spi_context *ctx = &data->ctx; in xlnx_quadspi_cs_control()
124 uint32_t spissr = BIT_MASK(config->num_ss_bits); in xlnx_quadspi_cs_control()
127 /* Skip slave select assert/de-assert in slave mode */ in xlnx_quadspi_cs_control()
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/Zephyr-latest/include/zephyr/drivers/
Dmspi.h4 * SPDX-License-Identifier: Apache-2.0
241 /** @brief GPIO chip-select line numbers (optional) */
247 /** @brief Whether to re-initialize controller */
281 /** @brief Configure number of clock cycles between
285 /** @brief Configure number of clock cycles between
291 /** @brief Configure write command */
392 /** @brief Configure TX dummy cycles */
394 /** @brief Configure RX dummy cycles */
400 /** @brief Hold CE active after xfer */
528 * re-initialize their controller hardware. Additional SoC platform specific
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/Zephyr-latest/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
34 * active.
36 * * Some devices support a Deep Power-Down mode which reduces current
40 * * PM_DEVICE_STATE_ACTIVE covers both active and standby modes;
41 * * PM_DEVICE_STATE_SUSPENDED corresponds to deep-power-down mode;
63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
66 /* MXICY Low-power/high perf mode is second bit in configuration register 2 */
72 /* Build-time data associated with the device. */
92 /* Expected JEDEC ID, from jedec-id property */
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/Zephyr-latest/subsys/fs/zms/
Dzms.c4 * SPDX-License-Identifier: Apache-2.0
33 /* 32-bit integer hash function found by https://github.com/skeeto/hash-prospector. */ in zms_lookup_cache_pos()
54 memset(fs->lookup_cache, 0xff, sizeof(fs->lookup_cache)); in zms_lookup_cache_rebuild()
55 addr = fs->ate_wra; in zms_lookup_cache_rebuild()
66 cache_entry = &fs->lookup_cache[zms_lookup_cache_pos(ate.id)]; in zms_lookup_cache_rebuild()
74 if (rc == -ENOENT) { in zms_lookup_cache_rebuild()
88 if (addr == fs->ate_wra) { in zms_lookup_cache_rebuild()
98 uint64_t *cache_entry = fs->lookup_cache; in zms_lookup_cache_invalidate()
99 uint64_t *const cache_end = &fs->lookup_cache[CONFIG_ZMS_LOOKUP_CACHE_SIZE]; in zms_lookup_cache_invalidate()
113 return fs->offset + (fs->sector_size * SECTOR_NUM(addr)) + SECTOR_OFFSET(addr); in zms_addr_to_offset()
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
180 * of non-standard values
203 /* Bit mask to access Transmit buffer index offset 10-bit field */
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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Drelease-notes-1.11.rst12 * Thread-level memory protection on x86, ARC and Arm, userspace and memory
15 * Initial Armv8-M architecture support.
20 * Firmware over-the-air (FOTA) updates over BLE using MCUmgr.
32 * SMP-aware scheduler
47 * Armv8-M initial architecture support, including the following cores:
49 * Arm Cortex-M23
50 * Arm Cortex-M33
74 * Refactored dts.fixup so common SoC-related fixes are in arch/<*>/soc
75 and board dts.fixup is only used for board-specific items.
82 * Added I2C master, QSPI flash, and GPIO drivers for nios-II
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Drelease-notes-2.1.rst13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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Drelease-notes-2.3.rst18 with future support for features like 64-bit and absolute timeouts in mind
21 * Zephyr now integrates with the TF-M (Trusted Firmware M) PSA-compliant
24 * The CMSIS-DSP library is now included and integrated
33 * CVE-2020-10022: UpdateHub Module Copies a Variable-Sized Hash String
34 into a fixed-size array.
35 * CVE-2020-10059: UpdateHub Module Explicitly Disables TLS
37 * CVE-2020-10061: Improper handling of the full-buffer case in the
39 * CVE-2020-10062: Packet length decoding error in MQTT
40 * CVE-2020-10063: Remote Denial of Service in CoAP Option Parsing Due
42 * CVE-2020-10068: In the Zephyr project Bluetooth subsystem, certain
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/Zephyr-latest/include/zephyr/
Dkernel.h4 * SPDX-License-Identifier: Apache-2.0
54 #define K_PRIO_COOP(x) (-(CONFIG_NUM_COOP_PRIORITIES - (x)))
57 #define K_HIGHEST_THREAD_PRIO (-CONFIG_NUM_COOP_PRIORITIES)
61 #define K_LOWEST_APPLICATION_THREAD_PRIO (K_LOWEST_THREAD_PRIO - 1)
246 * bits, arch-specific use high bits.
290 * from within a user-provided callback they have been invoked.
291 * Effectively it serves as a tiny bit of zero-overhead TLS data.
329 /* end - thread options */
336 * - @ref K_USER allocate a userspace thread (requires `CONFIG_USERSPACE=y`)
354 * @retval -EBUSY if the thread stack is in use.
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/Zephyr-latest/cmake/modules/
Dextensions.cmake1 # SPDX-License-Identifier: Apache-2.0
14 # 1. Zephyr-aware extensions
21 # 2. Kconfig-aware extensions
23 # 3. CMake-generic extensions
44 # 1. Zephyr-aware extensions
49 # "zephyr". zephyr is a catch-all CMake library for source files that
52 # [0] https://cmake.org/cmake/help/latest/manual/cmake-buildsystem.7.html
66 # As a very high-level introduction here are two call graphs that are
72 # zephyr_library_compile_options() --> target_compile_options()
75 # zephyr_cc_option() ---> target_cc_option()
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