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/Zephyr-Core-3.5.0/dts/riscv/ite/
Dit81xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpiogcr: gpio-gcr@f01600 {
12 compatible = "ite,it8xxx2-gpiogcr";
17 compatible = "ite,it8xxx2-gpiokscan";
23 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
25 gpio-controller;
26 #gpio-cells = <2>;
30 compatible = "ite,it8xxx2-gpiokscan";
36 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
38 gpio-controller;
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Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dite,it8xxx2-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 has-volt-sel:
19 wuc-base:
24 a wake-up signal to the INTC, allowing the CPU to exit
27 wuc-mask:
30 gpio-cells:
31 - pin
32 - flags
/Zephyr-Core-3.5.0/boards/arc/hsdk4xd/doc/
Dindex.rst10 It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces
19 (HSDK4xD) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
25 Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can prog…
26 ``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition f…
29 +--------+-------------+---------+--------------+---------------------------------+
31 +--------+-------------+---------+--------------+---------------------------------+
33 +--------+-------------+---------+--------------+---------------------------------+
35 +--------+-------------+---------+--------------+---------------------------------+
37 +--------+-------------+---------+--------------+---------------------------------+
39 +--------+-------------+---------+--------------+---------------------------------+
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/Zephyr-Core-3.5.0/boards/arc/hsdk/doc/
Dindex.rst9 The DesignWare(R) ARC(R) HS Development Kit is a ready-to-use platform for
11 single-core and multi-core ARC HS34, HS36 and HS38 processors and offers a wide
22 (HSDK) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
28 Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can prog…
29 CREG_GPIO_MUX register to do configuration for each sel. Tables below show the bit definition for
32 +--------+-------------+---------+--------------+---------------------------------+
34 +--------+-------------+---------+--------------+---------------------------------+
36 +--------+-------------+---------+--------------+---------------------------------+
38 +--------+-------------+---------+--------------+---------------------------------+
40 +--------+-------------+---------+--------------+---------------------------------+
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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