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/Zephyr-latest/lib/net_buf/
Dbuf_simple.c76 uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val) in net_buf_simple_add_u8() argument
80 NET_BUF_SIMPLE_DBG("buf %p val 0x%02x", buf, val); in net_buf_simple_add_u8()
83 *u8 = val; in net_buf_simple_add_u8()
88 void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_le16() argument
90 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_le16()
92 sys_put_le16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_le16()
95 void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val) in net_buf_simple_add_be16() argument
97 NET_BUF_SIMPLE_DBG("buf %p val %u", buf, val); in net_buf_simple_add_be16()
99 sys_put_be16(val, net_buf_simple_add(buf, sizeof(val))); in net_buf_simple_add_be16()
102 void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val) in net_buf_simple_add_le24() argument
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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h5_clock.h69 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG) argument
70 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR1_REG) argument
71 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG) argument
72 #define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR1_REG) argument
73 #define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR1_REG) argument
74 #define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR1_REG) argument
75 #define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 18, CCIPR1_REG) argument
76 #define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, CCIPR1_REG) argument
77 #define USART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR1_REG) argument
78 #define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 27, CCIPR1_REG) argument
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Dstm32n6_clock.h84 #define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG) argument
85 #define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG) argument
86 #define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) argument
88 #define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG) argument
89 #define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) argument
90 #define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG) argument
91 #define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG) argument
92 #define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG) argument
94 #define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) argument
95 #define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG) argument
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Dstm32u5_clock.h68 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) argument
69 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) argument
70 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG) argument
71 #define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR1_REG) argument
72 #define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR1_REG) argument
73 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) argument
74 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG) argument
75 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG) argument
76 #define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG) argument
77 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) argument
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Dstm32l4_clock.h52 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
53 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) argument
54 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) argument
55 #define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) argument
56 #define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) argument
57 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
58 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
59 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) argument
60 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) argument
61 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
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Dstm32f7_clock.h51 #define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) argument
52 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG) argument
53 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) argument
54 #define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG) argument
55 #define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG) argument
65 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) argument
73 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, DCKCFGR2_REG) argument
74 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, DCKCFGR2_REG) argument
75 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG) argument
76 #define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, DCKCFGR2_REG) argument
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Dstm32h7_clock.h75 #define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG) argument
76 #define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) argument
77 #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, D1CCIPR_REG) argument
78 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, D1CCIPR_REG) argument
79 #define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG) argument
81 #define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) argument
83 #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP1R_REG) argument
84 #define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, D2CCIP1R_REG) argument
85 #define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D2CCIP1R_REG) argument
86 #define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIP1R_REG) argument
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Dstm32f3_clock.h43 #define I2S_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG) argument
44 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG) argument
45 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG) argument
47 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) argument
48 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) argument
49 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 5, CFGR3_REG) argument
50 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) argument
51 #define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, CFGR3_REG) argument
52 #define TIM8_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 9, CFGR3_REG) argument
53 #define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 10, CFGR3_REG) argument
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Dstm32h7rs_clock.h74 #define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG) argument
75 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG) argument
76 #define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG) argument
77 #define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG) argument
78 #define OTGFS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG) argument
79 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG) argument
80 #define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG) argument
83 #define USART234578_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIPR_REG) argument
84 #define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, D2CCIPR_REG) argument
85 #define I2C23_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIPR_REG) argument
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Dstm32g4_clock.h51 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
52 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) argument
53 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) argument
54 #define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) argument
55 #define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) argument
56 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
57 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
58 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) argument
59 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) argument
60 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
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Dstm32g0_clock.h47 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
48 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) argument
49 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG) argument
50 #define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG) argument
51 #define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) argument
52 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
53 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
54 #define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) argument
55 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
56 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) argument
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Dstm32f410_clock.h17 #define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG) argument
18 #define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG) argument
19 #define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG) argument
20 #define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG) argument
21 #define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 25, DCKCFGR_REG) argument
22 #define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 27, DCKCFGR_REG) argument
23 #define CKDFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, DCKCFGR_REG) argument
26 #define I2CFMP1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG) argument
27 #define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG) argument
28 #define SDIO_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG) argument
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Dstm32u0_clock.h47 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
48 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) argument
49 #define LPUART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG) argument
50 #define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) argument
51 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
52 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
53 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) argument
54 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
55 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) argument
56 #define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) argument
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Dstm32wl_clock.h49 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
50 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG) argument
51 #define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) argument
52 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
53 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
54 #define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) argument
55 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) argument
56 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
57 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) argument
58 #define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) argument
[all …]
Dstm32wba_clock.h57 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) argument
58 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) argument
59 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) argument
60 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) argument
61 #define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) argument
62 #define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) argument
63 #define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG) argument
65 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) argument
67 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) argument
68 #define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG) argument
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Dstm32wb_clock.h52 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) argument
53 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG) argument
54 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) argument
55 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG) argument
56 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG) argument
57 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG) argument
58 #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG) argument
59 #define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG) argument
60 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG) argument
61 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) argument
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Dstm32f427_clock.h16 #define CKDFSDM2A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG) argument
17 #define CKDFSDM1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG) argument
18 #define SAI1A_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG) argument
19 #define SAI1B_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG) argument
20 #define CLK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR_REG) argument
21 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR_REG) argument
22 #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR_REG) argument
Dstm32f0_clock.h42 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) argument
43 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) argument
44 #define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) argument
45 #define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG) argument
46 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) argument
47 #define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) argument
49 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) argument
52 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) argument
53 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) argument
/Zephyr-latest/drivers/sensor/tdk/icm45686/
Dicm45686_reg.h67 #define REG_PWR_MGMT0_ACCEL_MODE(val) ((val) & BIT_MASK(2)) argument
68 #define REG_PWR_MGMT0_GYRO_MODE(val) (((val) & BIT_MASK(2)) << 2) argument
70 #define REG_ACCEL_CONFIG0_ODR(val) ((val) & BIT_MASK(4)) argument
71 #define REG_ACCEL_CONFIG0_FS(val) (((val) & BIT_MASK(3)) << 4) argument
73 #define REG_GYRO_CONFIG0_ODR(val) ((val) & BIT_MASK(4)) argument
74 #define REG_GYRO_CONFIG0_FS(val) (((val) & BIT_MASK(4)) << 4) argument
76 #define REG_DRIVE_CONFIG0_SPI_SLEW(val) (((val) & BIT_MASK(2)) << 1) argument
78 #define REG_MISC2_SOFT_RST(val) ((val << 1) & BIT(1)) argument
80 #define REG_IPREG_SYS1_REG_172_GYRO_LPFBW_SEL(val) (val & BIT_MASK(3)) argument
82 #define REG_IPREG_SYS2_REG_131_ACCEL_LPFBW_SEL(val) (val & BIT_MASK(3)) argument
[all …]
/Zephyr-latest/drivers/audio/
Dtas6422dac.c57 static void codec_write_reg(const struct device *dev, uint8_t reg, uint8_t val);
58 static void codec_read_reg(const struct device *dev, uint8_t reg, uint8_t *val);
121 uint8_t val; in codec_mute_output() local
131 codec_read_reg(dev, CH_STATE_CTRL_ADDR, &val); in codec_mute_output()
134 val &= ~CH_STATE_CTRL_CH1_STATE_CTRL_MASK; in codec_mute_output()
135 val |= CH_STATE_CTRL_CH1_STATE_CTRL(CH_STATE_CTRL_MUTE); in codec_mute_output()
138 val &= ~CH_STATE_CTRL_CH2_STATE_CTRL_MASK; in codec_mute_output()
139 val |= CH_STATE_CTRL_CH2_STATE_CTRL(CH_STATE_CTRL_MUTE); in codec_mute_output()
142 val &= ~(CH_STATE_CTRL_CH1_STATE_CTRL_MASK | CH_STATE_CTRL_CH2_STATE_CTRL_MASK); in codec_mute_output()
143 val |= CH_STATE_CTRL_CH1_STATE_CTRL(CH_STATE_CTRL_MUTE) | in codec_mute_output()
[all …]
/Zephyr-latest/drivers/sensor/pixart/paa3905/
Dpaa3905.c22 /* Helper struct used to set reg-val sequences for op-modes */
25 uint8_t val; member
91 uint8_t val = REG_BURST_READ | REG_SPI_READ_BIT; in paa3905_submit_one_shot() local
96 &val, in paa3905_submit_one_shot()
141 {.reg = 0x7F, .val = 0x00}, {.reg = 0x51, .val = 0xFF}, {.reg = 0x4E, .val = 0x2A}, in detection_mode_standard()
142 {.reg = 0x66, .val = 0x3E}, {.reg = 0x7F, .val = 0x14}, {.reg = 0x7E, .val = 0x71}, in detection_mode_standard()
143 {.reg = 0x55, .val = 0x00}, {.reg = 0x59, .val = 0x00}, {.reg = 0x6F, .val = 0x2C}, in detection_mode_standard()
144 {.reg = 0x7F, .val = 0x05}, {.reg = 0x4D, .val = 0xAC}, {.reg = 0x4E, .val = 0x32}, in detection_mode_standard()
145 {.reg = 0x7F, .val = 0x09}, {.reg = 0x5C, .val = 0xAF}, {.reg = 0x5F, .val = 0xAF}, in detection_mode_standard()
146 {.reg = 0x70, .val = 0x08}, {.reg = 0x71, .val = 0x04}, {.reg = 0x72, .val = 0x06}, in detection_mode_standard()
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/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h52 * @param val 16-bit integer in little-endian format.
60 * @param val 16-bit integer in host endianness.
68 * @param val 24-bit integer in little-endian format.
76 * @param val 24-bit integer in host endianness.
84 * @param val 32-bit integer in little-endian format.
92 * @param val 32-bit integer in host endianness.
100 * @param val 48-bit integer in little-endian format.
108 * @param val 48-bit integer in host endianness.
116 * @param val 16-bit integer in big-endian format.
124 * @param val 16-bit integer in host endianness.
[all …]
/Zephyr-latest/subsys/bluetooth/mesh/
Dsar_cfg.c42 uint8_t val; in bt_mesh_sar_tx_decode() local
44 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
45 tx->seg_int_step = (val & 0xf); in bt_mesh_sar_tx_decode()
46 tx->unicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
47 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
48 tx->unicast_retrans_without_prog_count = (val & 0xf); in bt_mesh_sar_tx_decode()
49 tx->unicast_retrans_int_step = (val >> 4); in bt_mesh_sar_tx_decode()
50 val = net_buf_simple_pull_u8(buf); in bt_mesh_sar_tx_decode()
51 tx->unicast_retrans_int_inc = (val & 0xf); in bt_mesh_sar_tx_decode()
52 tx->multicast_retrans_count = (val >> 4); in bt_mesh_sar_tx_decode()
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_ace_v1x_art.c19 uint32_t val; in counter_ace_v1x_art_ionte_set() local
21 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
22 val &= ~ACE_TSCTRL_IONTE_MASK; in counter_ace_v1x_art_ionte_set()
23 val |= FIELD_PREP(ACE_TSCTRL_IONTE_MASK, new_timestamp_enable); in counter_ace_v1x_art_ionte_set()
24 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_ionte_set()
29 uint32_t val; in counter_ace_v1x_art_cdmas_set() local
31 val = sys_read32(ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
32 val &= ~ACE_TSCTRL_CDMAS_MASK; in counter_ace_v1x_art_cdmas_set()
33 val |= FIELD_PREP(ACE_TSCTRL_CDMAS_MASK, cdmas); in counter_ace_v1x_art_cdmas_set()
34 sys_write32(val, ACE_TSCTRL); in counter_ace_v1x_art_cdmas_set()
[all …]
/Zephyr-latest/tests/drivers/sensor/generic/src/
Ddummy_sensor.c35 struct sensor_value *val) in dummy_sensor_channel_get() argument
41 val->val1 = data->val[0].val1; in dummy_sensor_channel_get()
42 val->val2 = data->val[0].val2; in dummy_sensor_channel_get()
45 val->val1 = data->val[1].val1; in dummy_sensor_channel_get()
46 val->val2 = data->val[1].val2; in dummy_sensor_channel_get()
49 val->val1 = data->val[2].val1; in dummy_sensor_channel_get()
50 val->val2 = data->val[2].val2; in dummy_sensor_channel_get()
53 val->val1 = data->val[3].val1; in dummy_sensor_channel_get()
54 val->val2 = data->val[3].val2; in dummy_sensor_channel_get()
57 val->val1 = data->val[4].val1; in dummy_sensor_channel_get()
[all …]

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