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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
[all …]
/Zephyr-latest/boards/digilent/arty_a7/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
32 compatible = "gpio-leds";
34 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
94 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
104 compatible = "gpio-keys";
116 gpios = <&gpio0_2 2 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/drivers/bluetooth/hci/
DKconfig.nxp2 # Copyright 2023-2024 NXP
4 # SPDX-License-Identifier: Apache-2.0
37 default 512
41 default 4
45 default 768
52 default "NXP"
55 default n
58 default 84
62 default 256
65 default y
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/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
54 uint32_t tri; member
60 /* Workaround to handle channel 2 interrupts from channel 1*/
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
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Dgpio_ite_it8xxx2_v2.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
19 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
80 const struct gpio_ite_cfg *gpio_config = dev->config; in gpio_ite_configure()
81 volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr; in gpio_ite_configure()
82 volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr; in gpio_ite_configure()
83 volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr; in gpio_ite_configure()
84 volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin; in gpio_ite_configure()
85 struct gpio_ite_data *data = dev->data; in gpio_ite_configure()
92 return -ENOTSUP; in gpio_ite_configure()
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Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
77 (volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) : in wuesr()
78 (volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5)); in wuesr()
82 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
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/Zephyr-latest/subsys/mgmt/osdp/
DKconfig.pd4 # SPDX-License-Identifier: Apache-2.0
11 default 1
18 default 16
26 default 1
38 default "NONE"
43 channel with default SCBK. Once as secure channel is active with the
44 default key, the CP can send a KEYSET command to set new keys to the PD.
54 default 0x001A2B3C
61 default 1
68 default 1
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/Zephyr-latest/soc/ite/ec/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
41 * Pin pull-up/down config [ 4 : 5 ]
44 * Pin push-pull/open-drain [ 16 ]
46 * Pin drive current default [ 21 ]
60 /* Pin tri-state mode. */
63 /* Pin pull-up or pull-down */
73 /* Pin push-pull/open-drain mode */
[all …]
/Zephyr-latest/drivers/spi/
Dspi_xlnx_axi_quadspi.c4 * SPDX-License-Identifier: Apache-2.0
20 /* AXI Quad SPI v3.2 register offsets (See Xilinx PG153 for details) */
39 #define SPICR_MASTER BIT(2)
51 #define SPISR_TX_EMPTY BIT(2)
73 #define IPIXR_DTR_EMPTY BIT(2)
105 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_read32()
107 return sys_read32(config->base + offset); in xlnx_quadspi_read32()
114 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_write32()
116 sys_write32(value, config->base + offset); in xlnx_quadspi_write32()
121 const struct xlnx_quadspi_config *config = dev->config; in xlnx_quadspi_cs_control()
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
85 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
100 uint8_t np; /* number of data pins: 1, 2, or 4 */
106 uint32_t tempbuf[2];
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
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Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t width; /* 1(single), 2(dual), 4(quad) */
43 ((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2); in descr_rd()
51 ((did & MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 2); in descr_wr()
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
103 * 2 1 0
129 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
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/Zephyr-latest/boards/nxp/frdm_rw612/doc/
Dindex.rst6 The RW612 is a highly integrated, low-power tri-radio wireless MCU with an
7 integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4
11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
15 operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply.
20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
21 - 1.2 MB on-chip SRAM
26 +-----------+------------+-----------------------------------+
29 | NVIC | on-chip | nested vector interrupt controller|
30 +-----------+------------+-----------------------------------+
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/doc/
Dindex.rst6 The RW612 is a highly integrated, low-power tri-radio wireless MCU with an
7 integrated 260 MHz ARM Cortex-M33 MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 / 802.15.4
11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
15 operation in a space- and cost-efficient wireless MCU requiring only a single 3.3 V power supply.
20 - 260 MHz ARM Cortex-M33, tri-radio cores for Wifi 6 + BLE 5.3 + 802.15.4
21 - 1.2 MB on-chip SRAM
26 +-----------+------------+-----------------------------------+
29 | NVIC | on-chip | nested vector interrupt controller|
30 +-----------+------------+-----------------------------------+
[all …]
/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
18 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
31 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U
34 /* Default SAF Map of eSPI TAG numbers to master numbers */
40 * Default QMSPI clock divider and chip select timing.
43 #define MCHP_SAF_QMSPI_CLK_DIV 2U
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
102 MCHP_QMSPI_C_XFR_NUNITS(2) | \
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/Zephyr-latest/dts/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21 pinctrl_uart1_default: uart1-default {
29 slew-rate = <IO_SPEED_SLOW>;
30 power-source = <IO_STANDARD_LVCMOS18>;
33 conf-rx {
35 bias-high-impedance;
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_SAF_MAX_FLASH_DEVICES 2U
30 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2u
33 /* Default SAF Map of eSPI TAG numbers to master numbers */
39 * Default QMSPI clock divider and chip select timing.
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
126 MCHP_QMSPI_C_XFR_NUNITS(2) | \
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/Zephyr-latest/drivers/wifi/nxp/
DKconfig.nxp1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP Wi-Fi driver support"
14 Enable NXP SoC Wi-Fi support.
25 default 50
28 bool "Custom NXP Wi-Fi part"
30 Customize NXP Wi-Fi chip support.
33 prompt "Select NXP Wi-Fi part"
36 Choose NXP Wi-Fi chip support.
39 bool "NXP RW610-based Chipset"
[all …]
/Zephyr-latest/boards/nxp/lpcxpresso11u68/doc/
Dindex.rst7 on an ARM Cortex-M0+ core.
14 - LPC11U68 microcontroller in LQFP100 package
15 - ARM Cortex-M0+
16 - Memory:
18 - 256KB of flash memory
19 - 32KB of SRAM
20 - 2x2KB of additional SRAM
21 - 4 KB EEPROM
22 - USB:
24 - USB 2.0 Full-Speed device controller
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxc444/doc/
Dindex.rst6 FRDM-MCXC444 is a compact and scalable development board for rapid
8 for easy access to the MCU's I/Os, integrated open-standard serial
9 interfaces and on-board MCU-Link debugger.
10 The MCXC is a general purpose ultra-low-power MCU family,
16 - MCXC444VLH Arm Cortex-M0+ microcontroller running at 48 MHz
17 - 64LQFP package
18 - 256 KB flash
19 - 32 KB SRAM
20 - USB FS 2.0
21 - 2x low-power UART, 1x UART, 2x I2C, 2x SPI
[all …]
/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.h3 * SPDX-License-Identifier: Apache-2.0
51 /* used to convert the clock-names property into an array of clock names */
72 /* used to convert a clock-names property into an array of clock names. If the
89 /* used to parse the tx-fifo-watermark property. If said property is not
95 FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2)
97 /* used to parse the rx-fifo-watermark property. If said property is not
103 FSL_FEATURE_SAI_FIFO_COUNTn(UINT_TO_I2S(DT_INST_REG_ADDR(inst))) / 2)
107 POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->TDR[idx]))
111 POINTER_TO_UINT(&(UINT_TO_I2S(DT_INST_REG_ADDR(inst))->RDR[idx]))
113 /* internal macro used to retrieve the default TX/RX FIFO's size (in FIFO words) */
[all …]
/Zephyr-latest/scripts/kconfig/
Dguiconfig.py4 # SPDX-License-Identifier: ISC
10 # pylint: disable=undefined-variable
16 A Tkinter-based menuconfig implementation, based around a treeview control and
18 ('make xconfig'). Compatible with both Python 2 and Python 3.
21 single menu (like menuconfig.py). Only single-menu mode distinguishes between
24 A show-all mode is available that shows invisible items in red.
29 Ctrl-S : Save configuration
30 Ctrl-O : Open configuration
31 Ctrl-A : Toggle show-all mode
32 Ctrl-N : Toggle show-name mode
[all …]
/Zephyr-latest/boards/nxp/frdm_kl25z/doc/
Dindex.rst6 The Freedom KL25Z is an ultra-low-cost development platform for
8 on ARM |reg| Cortex |reg|-M0+ processor.
10 The FRDM-KL25Z features include easy access to MCU I/O, battery-ready,
11 low-power operation, a standard-based form factor with expansion board
12 options and a built-in debug interface for flash programming and run-control.
17 - MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP
18 - On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED
19 - OpenSDA debug interface
21 For more information about the KL25Z SoC and FRDM-KL25Z board:
23 - `KL25Z Website`_
[all …]
/Zephyr-latest/boards/nxp/frdm_k82f/doc/
Dindex.rst6 The FRDM-K82F is a low-cost development platform for Kinetis K80, K81,
9 - Form-factor compatible with the Arduino R3 pin layout
10 - Peripherals enable rapid prototyping, including a six-axis digital
12 tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb
14 with Bluetooth and 2.4 GHz radio add-on modules
15 - OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter
17 flash programming, and run-control debugging
22 - MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power,
23 crystal-less USB, and 100 Low profile Quad Flat Package (LQFP))
24 - Dual role USB interface with micro-B USB connector
[all …]
/Zephyr-latest/boards/nxp/frdm_k22f/doc/
Dindex.rst6 The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22
9 - Form-factor compatible with the Arduino R3 pin layout
10 - Peripherals enable rapid prototyping, including a 6-axis digital
12 tri-colored LED and 2 user push-buttons for direct interaction, a optional
14 add-on modules
15 - OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
17 flash programming, and run-control debugging
22 - MK22FN512VLH12 (120 MHz, 512 KB flash memory, 128 KB RAM, low-power,
23 crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP))
24 - Dual role USB interface with micro-B USB connector
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
25 #include "i2c-priv.h"
29 #define SPEED_1MHZ_BUS 2
69 #define I2C_XEC_STATE_OPEN 2U
73 #define I2C_XEC_ERR_BUS 2
112 * i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
113 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
114 * (16MHz/400KHz -2) = 0x0F + 0x17
115 * (16MHz/1MHz -2) = 0x05 + 0x09
144 (const struct i2c_xec_config *const) (dev->config); in i2c_ctl_wr()
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