Searched full:transfers (Results 1 – 25 of 140) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | gd,gd32-dma.yaml | 17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
21 - 0x0: no address increase between transfers
22 - 0x1: increase address between transfers
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| D | st,stm32u5-dma.yaml | 31 0x0: no address increment between transfers
32 0x1: increment address between transfers
34 0x0: no address increment between transfers
35 0x1: increment address between transfers
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| D | gd,gd32-dma-v1.yaml | 19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
23 - 0x0: no address increase between transfers
24 - 0x1: increase address between transfers
80 A single burst transfer transfers [(4 * fifo-threshold)] bytes using with DMA's FIFO.
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| D | st,stm32-dma-v1.yaml | 14 this value is 0 for Memory-to-memory transfers
25 0x0: no address increment between transfers
26 0x1: increment address between transfers
28 0x0: no address increment between transfers
29 0x1: increment address between transfers
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| D | st,stm32-dma-v2.yaml | 17 this value is 0 for Memory-to-memory transfers
32 0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
33 0x1: STM32_DMA_PERIPH_INC: increment address between transfers
35 0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
36 0x1: STM32_DMA_MEM_INC: increment address between transfers
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| D | st,stm32-dmamux.yaml | 21 0x0: no address increment between transfers
22 0x1: increment address between transfers
24 0x0: no address increment between transfers
25 0x1: increment address between transfers
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| D | st,stm32-bdma.yaml | 23 0x0: no address increment between transfers
24 0x1: increment address between transfers
26 0x0: no address increment between transfers
27 0x1: increment address between transfers
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| D | st,stm32-dma-v2bis.yaml | 26 0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
27 0x1: STM32_DMA_PERIPH_INC: increment address between transfers
29 0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
30 0x1: STM32_DMA_MEM_INC: increment address between transfers
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | Kconfig.sc18im704 | 22 bool "Verify SC18IM704 I2C transfers"
25 Verify the I2C state register after I2C transfers to detect errors.
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| D | Kconfig.dw | 22 data transfers. All Tx operaton are done using dma channel 0 and
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| /Zephyr-Core-3.5.0/drivers/usb/uhc/ |
| D | Kconfig | 15 int "Number of transfers in the pool"
19 Number of UHC transfers available.
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| /Zephyr-Core-3.5.0/dts/bindings/i3c/ |
| D | i3c-controller.yaml | 23 Frequency of the SCL signal used for I3C transfers. When undefined,
29 Frequency of the SCL signal used for I2C transfers. When undefined
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| /Zephyr-Core-3.5.0/samples/drivers/audio/dmic/ |
| D | README.rst | 5 Perform PDM transfers using different configurations.
12 It performs two PDM transfers with different configurations (using one channel
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| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | dma_pl330.h | 19 * b0001 = 2 data transfers
20 * b0010 = 3 data transfers
23 * b1111 = 16 data transfers
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| /Zephyr-Core-3.5.0/samples/drivers/spi_flash/boards/ |
| D | b_u585i_iot02a.overlay | 8 /* channel 12-15 are for transfers to/from external memories */
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/api/mesh/ |
| D | dfu_cli.rst | 8 transfers.
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | Kconfig.xmc4xxx | 24 Enables DMA for SPI transfers.
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| D | spi_rv32m1_lpspi.c | 79 /* Break up the tx into multiple transfers so we don't have to in spi_mcux_transfer_next_packet()
81 * active between transfers. in spi_mcux_transfer_next_packet()
88 /* Break up the rx into multiple transfers so we don't have to in spi_mcux_transfer_next_packet()
90 * active between transfers. in spi_mcux_transfer_next_packet()
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| /Zephyr-Core-3.5.0/subsys/usb/device/ |
| D | Kconfig | 63 Allocates buffers used for parallel transfers. Increase this number
136 offloaded transfers.
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| /Zephyr-Core-3.5.0/tests/drivers/i2s/i2s_api/ |
| D | Kconfig | 17 bool "Use I2S_DIR_BOTH value to perform RX/TX transfers"
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| /Zephyr-Core-3.5.0/tests/drivers/i2s/i2s_speed/ |
| D | Kconfig | 17 bool "Use I2S_DIR_BOTH value to perform RX/TX transfers"
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| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/ |
| D | cpu.h | 21 * Implementation: In the Cortex-M processors data transfers are in cpu_dmb()
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | nxp,lpc-spi.yaml | 33 Delay in nanoseconds inserted between transfers when chip select is
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| /Zephyr-Core-3.5.0/tests/drivers/dma/loop_transfer/src/ |
| D | test_dma_loop.c | 255 /* Try multiple times to suspend the transfers */ in test_loop_suspend_resume()
274 TC_PRINT("ERROR: failed to suspend transfers\n"); in test_loop_suspend_resume()
280 TC_PRINT("suspended after %d transfers occurred\n", transfer_count); in test_loop_suspend_resume()
287 TC_PRINT("ERROR: failed to suspend transfers\n"); in test_loop_suspend_resume()
293 TC_PRINT("resuming after %d transfers occurred\n", transfer_count); in test_loop_suspend_resume()
296 TC_PRINT("Resumed transfers\n"); in test_loop_suspend_resume()
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| /Zephyr-Core-3.5.0/include/zephyr/bluetooth/mesh/ |
| D | blob_srv.h | 95 * Server will not accept any new transfers.
114 * Transfers will not be resumed after a reboot if this callback is not
165 * incoming transfers with a matching BLOB ID.
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