| /Zephyr-Core-3.6.0/tests/drivers/can/timing/src/ |
| D | main.c | 25 * @brief Defines a set of CAN timing test values
32 /** Do these values represent an invalid CAN timing? */
37 * @brief List of CAN timing values to test.
61 * @brief List of CAN timing values to test for the data phase.
79 * @brief Assert that a CAN timing struct matches the specified bitrate
81 * Assert that the values of a CAN timing struct matches the specified bitrate
85 * @param timing pointer to the CAN timing struct
88 static void assert_bitrate_correct(const struct device *dev, struct can_timing *timing, in assert_bitrate_correct() argument
91 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2; in assert_bitrate_correct()
96 zassert_not_equal(timing->prescaler, 0, "prescaler is zero"); in assert_bitrate_correct()
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| /Zephyr-Core-3.6.0/include/zephyr/timing/ |
| D | timing.h | 11 #include <zephyr/timing/types.h>
18 * @brief Timing Measurement APIs
19 * @defgroup timing_api Timing Measurement APIs
22 * The timing measurement APIs can be used to obtain execution
25 * Please note that the timing functions may use a different timer
31 * @brief SoC specific Timing Measurement APIs
32 * @defgroup timing_api_soc SoC specific Timing Measurement APIs
35 * Implements the necessary bits to support timing measurement
36 * using SoC specific timing measurement mechanism.
42 * @brief Initialize the timing subsystem on SoC.
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/usb_c/ |
| D | usbc_tc.h | 45 * See Table 4-29 VBUS and VCONN Timing Parameters
52 * See Table 4-29 VBUS and VCONN Timing Parameters
58 * See Table 4-29 VBUS and VCONN Timing Parameters
65 * See Table 4-29 VBUS and VCONN Timing Parameters
72 * See Table 4-29 VBUS and VCONN Timing Parameters
79 * See Table 4-29 VBUS and VCONN Timing Parameters
85 * See Table 4-30 DRP Timing Parameters
91 * See Table 4-30 DRP Timing Parameters
98 * See Table 4-30 DRP Timing Parameters
105 * See Table 4-30 DRP Timing Parameters
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| /Zephyr-Core-3.6.0/doc/kernel/timing_functions/ |
| D | index.rst | 6 The timing functions can be used to obtain execution time of
9 Please note that the timing functions may use a different timer
16 To allow using the timing functions, :kconfig:option:`CONFIG_TIMING_FUNCTIONS`
22 To gather timing information:
27 timing information. This usually starts the timer.
41 7. Repeat from step 3 to gather timing information for other
45 timing information. This usually stops the timer.
50 This shows an example on how to use the timing functions:
54 #include <zephyr/timing/timing.h>
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| /Zephyr-Core-3.6.0/subsys/timing/ |
| D | Kconfig | 6 bool "Timing Functions"
8 When enabled, timing related functions are compiled. This is
9 useful for gathering timing on code execution.
15 Hidden option to indicate that timing functions need to be
19 to use timing functions.
|
| /Zephyr-Core-3.6.0/drivers/w1/ |
| D | w1_zephyr_gpio.c | 14 * follows the timing specifications for 1-Wire communication.
35 * The time critical sections are used to ensure that the timing
49 * Standard timing between communication operations:
63 * Overdrive timing between communication operations:
103 /** timing parameters for 1-Wire communication */
104 const struct w1_gpio_timing *timing; member
141 const struct w1_gpio_timing *timing = data->timing; in w1_gpio_reset_bus() local
146 W1_GPIO_WAIT_US(timing->g); in w1_gpio_reset_bus()
152 W1_GPIO_WAIT_US(timing->h); in w1_gpio_reset_bus()
158 W1_GPIO_WAIT_US(timing->i); in w1_gpio_reset_bus()
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| /Zephyr-Core-3.6.0/dts/bindings/can/ |
| D | can-fd-controller.yaml | 16 This property is required unless the timing is specified using time quanta based properties
19 If this property is present, the time quanta based timing properties are ignored.
28 timing parameters. Default of 1 matches the default value previously used for all in-tree CAN
31 Applications can still manually set the SJW using the CAN timing APIs.
37 favor of setting advanced timing parameters from the application.
43 in favor of setting advanced timing parameters from the application.
49 in favor of setting advanced timing parameters from the application.
|
| D | can-controller.yaml | 16 This property is required unless the timing is specified using time quanta based properties
19 If this property is present, the time quanta based timing properties are ignored.
28 timing parameters. Default of 1 matches the default value previously used for all in-tree CAN
31 Applications can still manually set the SJW using the CAN timing APIs.
37 advanced timing parameters from the application.
43 advanced timing parameters from the application.
49 advanced timing parameters from the application.
|
| /Zephyr-Core-3.6.0/dts/bindings/memory-controllers/ |
| D | atmel,sam-smc.yaml | 27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
37 55ns, as per specification, it requires atmel,smc-cycle-timing of at least
38 7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
43 Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
47 cycle-timing (7) = setup (1) + pulse (6) + hold (0)
50 cycle-timing (10) = setup (1) + pulse (6) + hold (3)
117 atmel,smc-setup-timing:
129 atmel,smc-pulse-timing:
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| D | st,stm32-fmc-nor-psram.yaml | 63 st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
108 * WAITCFG - Wait timing configuration.
112 If set, then 'st,timing-ext' shall be provided.
120 st,timing:
124 SRAM/NOR-Flash (read) timing register (FMC_BTRx).
129 'st,timing-ext' to configure write accesses.
172 st,timing-ext:
176 SRAM/NOR-Flash (write) timing register (FMC_BWTRx).
191 Refer to 'st,timing' for detailed field descriptions.
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| /Zephyr-Core-3.6.0/drivers/can/ |
| D | can_common.c | 82 * @brief Update the timing given a total number of time quanta and a sample point.
102 * @param max Maximum timing parameters values.
103 * @param min Minimum timing parameters values.
261 int can_calc_prescaler(const struct device *dev, struct can_timing *timing, in can_calc_prescaler() argument
264 uint32_t ts = timing->prop_seg + timing->phase_seg1 + timing->phase_seg2 + in can_calc_prescaler()
274 timing->prescaler = core_clock / (bitrate * ts); in can_calc_prescaler()
276 return core_clock % (ts * timing->prescaler); in can_calc_prescaler()
303 static int check_timing_in_range(const struct can_timing *timing, in check_timing_in_range() argument
307 if (!IN_RANGE(timing->sjw, min->sjw, max->sjw) || in check_timing_in_range()
308 !IN_RANGE(timing->prop_seg, min->prop_seg, max->prop_seg) || in check_timing_in_range()
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| D | can_shell.c | 349 shell_print(sh, "timing: sjw %u..%u, prop_seg %u..%u, " in cmd_can_show()
361 shell_print(sh, "timing data: sjw %u..%u, prop_seg %u..%u, " in cmd_can_show()
391 struct can_timing timing = { 0 }; in cmd_can_bitrate_set() local
415 err = can_calc_timing(dev, &timing, bitrate, sample_pnt); in cmd_can_bitrate_set()
417 shell_error(sh, "failed to calculate timing for " in cmd_can_bitrate_set()
425 timing.sjw = (uint16_t)strtoul(argv[4], &endptr, 10); in cmd_can_bitrate_set()
435 timing.sjw); in cmd_can_bitrate_set()
438 timing.sjw, timing.prop_seg, timing.phase_seg1, timing.phase_seg2, in cmd_can_bitrate_set()
439 timing.prescaler); in cmd_can_bitrate_set()
441 err = can_set_timing(dev, &timing); in cmd_can_bitrate_set()
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| D | can_mcux_flexcan.c | 141 struct can_timing timing; member
162 const struct can_timing *timing) in mcux_flexcan_set_timing() argument
166 if (!timing) { in mcux_flexcan_set_timing()
174 data->timing = *timing; in mcux_flexcan_set_timing()
270 flexcan_timing_config_t timing; in mcux_flexcan_start() local
313 /* Delay this until start since setting the timing automatically exits freeze mode */ in mcux_flexcan_start()
314 timing.preDivider = data->timing.prescaler - 1U; in mcux_flexcan_start()
315 timing.rJumpwidth = data->timing.sjw - 1U; in mcux_flexcan_start()
316 timing.phaseSeg1 = data->timing.phase_seg1 - 1U; in mcux_flexcan_start()
317 timing.phaseSeg2 = data->timing.phase_seg2 - 1U; in mcux_flexcan_start()
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| /Zephyr-Core-3.6.0/drivers/i2c/ |
| D | i2c_xilinx_axi.h | 30 REG_TSUSTA = 0x128, /* Timing Parameter */
31 REG_TSUSTO = 0x12C, /* Timing Parameter */
32 REG_THDSTA = 0x130, /* Timing Parameter */
33 REG_TSUDAT = 0x134, /* Timing Parameter */
34 REG_TBUF = 0x138, /* Timing Parameter */
35 REG_THIGH = 0x13C, /* Timing Parameter */
36 REG_TLOW = 0x140, /* Timing Parameter */
37 REG_THDDAT = 0x144, /* Timing Parameter */
|
| /Zephyr-Core-3.6.0/dts/bindings/i2c/ |
| D | st,stm32-i2c-v2.yaml | 26 An optional table of pre-computed i2c timing values with the
33 Because timing value is valid for a given I2C peripheral clock
34 frequency and target I2C bus clock, each timing value must be
38 clock-frequency timing>
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| /Zephyr-Core-3.6.0/tests/subsys/sd/sdio/src/ |
| D | main.c | 71 TC_PRINT("Card timing: SDR12\n"); in ZTEST()
74 TC_PRINT("Card timing: SDR25\n"); in ZTEST()
77 TC_PRINT("Card timing: SDR50\n"); in ZTEST()
80 TC_PRINT("Card timing: SDR104\n"); in ZTEST()
83 TC_PRINT("Card timing: DDR50\n"); in ZTEST()
86 zassert_unreachable("Card timing is not known value"); in ZTEST()
|
| /Zephyr-Core-3.6.0/tests/arch/common/timing/ |
| D | testcase.yaml | 7 arch.common.timing:
9 - timing
|
| /Zephyr-Core-3.6.0/tests/kernel/sleep/ |
| D | testcase.yaml | 2 kernel.common.timing:
6 kernel.common.timing.minimallibc:
|
| /Zephyr-Core-3.6.0/tests/benchmarks/latency_measure/src/ |
| D | timing_sc.h | 11 #include <zephyr/timing/timing.h>
|
| /Zephyr-Core-3.6.0/doc/hardware/peripherals/can/ |
| D | shell.rst | 31 timing for the CAN FD data phase).
65 RX filters supported, capabilities, current mode, current state, error counters, timing limits, and
80 … timing: sjw 1..128, prop_seg 0..0, phase_seg1 2..256, phase_seg2 2..128, prescaler 1..512
81 timing data: sjw 1..16, prop_seg 0..0, phase_seg1 1..32, phase_seg2 1..16, prescaler 1..32
99 The CAN shell allows for configuring the CAN controller mode and timing, along with starting and
103 The CAN controller mode and timing can only be changed while the CAN controller is stopped, which
105 initial timing is set according to the ``bus-speed``, ``sample-point``, ``bus-speed-data``, and
108 Timing subsection
131 It is also possible to configure the raw bit timing using the ``can timing`` and ``can dtiming``
153 After the timing and mode has been configured as needed, the CAN controller can be started using the
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| /Zephyr-Core-3.6.0/dts/bindings/w1/ |
| D | w1-slave.yaml | 18 Instead of standard speed timing, use overdrive speed timing for
|
| /Zephyr-Core-3.6.0/soc/arm/microchip_mec/mec1501/ |
| D | CMakeLists.txt | 18 # Use MEC15xx timing calculations only if DWT is not present
20 zephyr_library_sources(timing.c)
|
| /Zephyr-Core-3.6.0/dts/bindings/sensor/ |
| D | ams,tsl2561.yaml | 16 ADC integration time in ms. The default value matches Timing Register's value at power on.
25 ADC gain factor. The default value matches Timing Register's value at power on.
|
| /Zephyr-Core-3.6.0/soc/arm/microchip_mec/mec172x/ |
| D | CMakeLists.txt | 18 # Use MEC172x timing calculations only if DWT is not present
20 zephyr_library_sources(timing.c)
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| /Zephyr-Core-3.6.0/tests/drivers/disk/disk_performance/src/ |
| D | main.c | 12 #include <zephyr/timing/timing.h>
92 /* Start the timing system */ in read_helper()
110 /* Stop timing system */ in read_helper()
145 /* Start the timing system */ in write_helper()
169 /* Stop timing system */ in write_helper()
219 /* Start the timing system */ in ZTEST()
235 /* Stop timing system */ in ZTEST()
270 /* Start the timing system */ in ZTEST()
287 /* Stop timing system */ in ZTEST()
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