Searched full:timebase (Results 1 – 20 of 20) sorted by relevance
| /Zephyr-Core-3.5.0/drivers/watchdog/ |
| D | Kconfig.xlnx | 7 bool "Xilinx AXI Timebase WDT driver"
11 Enable the Xilinx AXI Timebase WDT driver.
16 bool "Expose HWINFO API in Xilinx AXI Timebase WDT driver"
20 Controls whether the Xilinx AXI Timebase WDT driver exposes a HWINFO
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| D | wdt_xilinx_axi.c | 2 * Driver for Xilinx AXI Timebase WDT core, as described in
25 REG_TBR = 0x08, /* Timebase Register */
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 8 require to use a reference timebase from a master bus.
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
52 OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
91 A phandle to master-bus node that will be used as external timebase
94 is used as a timebase for a channel in SAIC mode, do not use that
95 master bus as a timebase for generate PWM pulse.
108 at runtime will impact to all channels share the same timebase.
114 at runtime will impact to all channels share the same timebase,
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| /Zephyr-Core-3.5.0/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 8 as a reference timebase (master bus) for other channels.
47 For example, to enable bus A of eMIOS instance 0 that can be used as timebase
74 as timebase for the operation, lsb is channel 0. The mask bit for this master bus
112 for channels use this bus as reference timebase. Could be in range [2 ... 65535]
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| /Zephyr-Core-3.5.0/dts/bindings/watchdog/ |
| D | xlnx,xps-timebase-wdt-1.00.a.yaml | 4 description: Xilinx AXI timebase WDT core
6 compatible: "xlnx,xps-timebase-wdt-1.00.a"
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/watchdog/boards/ |
| D | qemu_cortex_m3.overlay | 9 compatible = "xlnx,xps-timebase-wdt-1.00.a";
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| /Zephyr-Core-3.5.0/dts/riscv/lowrisc/ |
| D | opentitan_earlgrey.dtsi | 15 timebase-frequency = <10000000>;
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| /Zephyr-Core-3.5.0/dts/riscv/efinix/ |
| D | sapphire_soc.dtsi | 35 timebase-frequency = <100000000>;
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| /Zephyr-Core-3.5.0/dts/riscv/ |
| D | virt.dtsi | 39 timebase-frequency = < 10000000 >;
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| D | riscv32-litex-vexriscv.dtsi | 28 timebase-frequency = <32768>;
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| /Zephyr-Core-3.5.0/boards/arm/mr_canhubk3/ |
| D | mr_canhubk3.dts | 425 * Timebase for PWM led, setting clock 50KHz for internal counter,
530 * Timebase for PWM led, setting clock 50KHz for internal counter,
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| /Zephyr-Core-3.5.0/dts/riscv/starfive/ |
| D | starfive_jh7100_beagle_v.dtsi | 19 timebase-frequency = <6250000>;
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| /Zephyr-Core-3.5.0/drivers/adc/ |
| D | adc_gecko.c | 59 init.timebase = ADC_TimebaseCalc(0); in adc_gecko_set_config()
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| /Zephyr-Core-3.5.0/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 18 timebase-frequency = <60000000>;
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_nxp_s32_emios.c | 565 * If timebase is configured in MCB up/down count mode: pwm period = (2 * master bus's period - 2)
721 .Timebase = COND_CODE_1(DT_NODE_HAS_PROP(node_id, master_bus), \
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| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | stm32_lptim_timer.c | 236 /* maximise to TIMEBASE */ in sys_clock_set_timeout()
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| /Zephyr-Core-3.5.0/drivers/ieee802154/ |
| D | ieee802154_dw1000_regs.h | 862 /* External timebase reset mode enable */
866 * external timebase reset
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| D | ieee802154_kw41z.c | 1000 /* Set prescaler to obtain 1 symbol (16us) timebase */ in kw41z_init()
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| D | ieee802154_mcr20a.c | 350 LOG_DBG("done, timebase %d", tb); in mcr20a_timer_init()
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| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-3.2.rst | 1498 * Used consistent timebase in ``sem_timedwait()``.
2309 * :github:`46807` - lib: posix: semaphore: use consistent timebase in sem_timedwait
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